.1 Revision | 2.2 | Block Diagram |
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| IEEE 1588 |
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| Time Stamp |
Datasheet | Performance High |
| Managed 10/100 Port Two |
21 DATASHEET
To Ethernet |
| MII |
10/100 |
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| PHY | MDIO |
| Registers |
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| IEEE 1588 | |
| Time Stamp | |
To Ethernet |
| MII |
10/100 |
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| PHY | MDIO |
Registers
1Port | 10/100 | Queues4 | Dynamic QoS | Queues4 | Dynamic QoS |
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| MAC |
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| Switch Engine |
| Search | |
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| Engine | ||
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| Buffer Manager |
| Frame | |
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| Queues4 |
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| Buffers |
2Port | 10/100 | Dynamic QoS |
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| MAC |
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| Switch Fabric |
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MAC | 0Port |
10/100 |
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IEEE 1588
Time Stamp
Switch
Registers
(CSRs)
System
Registers
(CSRs)
MII | MDIO | MDIO |
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Host MAC
TX/RX FIFOs
Register 
Access
MUX
Virtual PHY
Registers
MDIO
Host Bus Interface 
To
Host Bus
EEPROM Loader
Interface CPU |
SMSC
GPIO/LED | IEEE 1588 | System | System | GP Timer | EEPROM Controller | I2C/Microwire |
Time Stamp | Interrupt | Clocks/ |
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Controller | Reset/PME |
| I2C (master) |
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Clock/Events | Controller | Microwire (master) | To optional | |||
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| Controller | Clk |
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LAN9312 |
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| EEPROM |
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To optional GPIOs/LEDs |
| IRQ | External |
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| 25MHz Crystal |
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Figure 2.1 Internal LAN9312 Block Diagram
LAN9312