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SMSC LAN9312 manual 11

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Chapter 16 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

16.1 128-VTQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 16.2 128-XVTQFP Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Chapter 17 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

SMSC LAN9312

11

Revision 1.4 (08-19-08)

 

DATASHEET

 

Contents
LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCICPU Interface Page Table of Contents Page Page Page Page Page Page Page Page List of Figures Page List of Tables Page Chapter 1 Preface 1.1General Terms Page 1.2Buffer Types 1.3Register Nomenclature Chapter 2 Introduction 2.1General Description Block Diagram 2.2.1System Clocks/Reset/PME Controller 2.2.2System Interrupt Controller 2.2.3Switch Fabric 2.2.4Ethernet PHYs 2.2.5Host Bus Interface (HBI) 2.2.6Host MAC 2.2.7EEPROM Controller/Loader 2.2.81588 Time Stamp 2.2.9GPIO/LED Controller 2.3System Configuration Chapter 3 Pin Description and Configuration 3.1Pin Diagrams 3.1.1128-VTQFPPin Diagram 3.1.2128-XVTQFPPin Diagram 3.2Pin Descriptions Page Page Page Page Page Page Page Chapter 4 Clocking, Resets, and Power Management 4.1Clocks 4.2Resets 4.2.1Chip-LevelResets 4.2.2Multi-ModuleResets 4.2.3Single-ModuleResets 4.2.4Configuration Straps Page Page Page Page 4.2.4.2Hard-Straps 4.3Power Management 4.3.1Port 1 & 2 PHY Power Management 4.3.2Host MAC Power Management Chapter 5 System Interrupts 5.1Functional Overview 5.2Interrupt Sources Page 5.2.11588 Time Stamp Interrupts 5.2.2Switch Fabric Interrupts 5.2.3Ethernet PHY Interrupts 5.2.4GPIO Interrupts 5.2.5Host MAC Interrupts 5.2.6Power Management Interrupts 5.2.7General Purpose Timer Interrupt 5.2.8Software Interrupt 5.2.9Device Ready Interrupt Chapter 6 Switch Fabric 6.1Functional Overview 6.2Switch Fabric CSRs 6.2.1Switch Fabric CSR Writes 6.2.2Switch Fabric CSR Reads 6.2.3Flow Control Enable Logic Page 6.310/100 Ethernet MACs 6.3.1Receive MAC 6.3.1.1Receive Counters 6.3.2Transmit MAC 6.4Switch Engine (SWE) 6.4.1MAC Address Lookup Table 6.4.1.1Learning/Aging/Migration 6.4.1.2Static Entries 6.4.1.3Multicast Pruning 6.4.1.4Address Filtering 6.4.1.5Spanning Tree Port State Override Page 6.4.2Forwarding Rules 6.4.3Transmit Priority Queue Selection Page 6.4.3.1Port Default Priority 6.4.3.2IP Precedence Based Priority 6.4.3.3DIFFSERV Based Priority 6.4.3.4VLAN Priority 6.4.4VLAN Support 6.4.5Spanning Tree Support 6.4.6Ingress Flow Metering and Coloring 6.4.6.1Ingress Flow Calculation Page 6.4.7Broadcast Storm Control 6.4.8IPv4 IGMP / IPv6 MLD Support 6.4.9Port Mirroring 6.4.10Host CPU Port Special Tagging 6.4.11Counters 6.5Buffer Manager (BM) 6.5.1Packet Buffer Allocation 6.5.2Random Early Discard (RED) 6.5.3Transmit Queues 6.5.4Transmit Priority Queue Servicing 6.5.5Egress Rate Limiting (Leaky Bucket) 6.5.6Adding, Removing, and Changing VLAN Tags Page 6.5.7Counters 6.6Switch Fabric Interrupts Chapter 7 Ethernet PHYs 7.1Functional Overview 7.1.1PHY Addressing 7.2Port 1 & 2 PHYs 7.2.1100BASE-TXTransmit Page 7.2.1.3Scrambler and PISO 7.2.1.4NRZI and MLT-3Encoding 7.2.1.5100M Transmit Driver 7.2.1.6100M Phase Lock Loop (PLL) 7.2.2100BASE-TXReceive 7.2.2.3NRZI and MLT-3Decoding 7.2.2.4Descrambler and SIPO 7.2.2.55B/4B Decoding 7.2.2.6Receiver Errors 7.2.2.7MII MAC Interface 7.2.310BASE-TTransmit 7.2.410BASE-TReceive 7.2.5PHY Auto-negotiation Page 7.2.5.1PHY Pause Flow Control 7.2.5.2Parallel Detection 7.2.5.3Restarting Auto-Negotiation 7.2.5.4Disabling Auto-Negotiation 7.2.6HP Auto-MDIX 7.2.7MII MAC Interface 7.2.8PHY Management Control 7.2.9PHY Power-DownModes 7.2.10PHY Resets 7.2.11LEDs 7.2.12Required Ethernet Magnetics 7.3Virtual PHY 7.3.1Virtual PHY Auto-Negotiation 7.3.1.1Parallel Detection 7.3.1.2Disabling Auto-Negotiation 7.3.2Virtual PHY Resets Chapter 8 Host Bus Interface (HBI) 8.1Functional Overview 8.2Host Memory Mapping 8.3Host Endianess Page 8.4Host Interface Timing 8.4.1Special Situations 8.4.2Special Restrictions on Back-toBack Write-ReadCycles Page Page Page 8.4.3Special Restrictions on Back-to-BackRead Cycles 8.4.4PIO Reads 8.4.5PIO Burst Reads 8.4.6RX Data FIFO Direct PIO Reads 8.4.7RX Data FIFO Direct PIO Burst Reads 8.4.8PIO Writes 8.4.9TX Data FIFO Direct PIO Writes 8.5HBI Interrupts Chapter 9 Host MAC 9.1Functional Overview 9.2Flow Control 9.2.1Full-DuplexFlow Control 9.2.2Half-DuplexFlow Control (Backpressure) 9.3Virtual Local Area Network (VLAN) Support 9.4Address Filtering 9.4.1Perfect Filtering 9.4.2Hash Only Filtering 9.4.3Hash Perfect Filtering 9.4.4Inverse Filtering 9.5Wake-upFrame Detection Page 9.5.1Magic Packet Detection 9.6Host MAC Address 9.7FIFOs 9.7.1TX/RX FIFOs 9.7.2MIL FIFOs 9.7.3FIFO Memory Allocation Configuration 9.8TX Data Path Operation Page 9.8.1TX Buffer Format 9.8.2TX Command Format TX Command ‘A’ 9.8.3TX Data Format 9.8.4TX Status Format 9.8.5Calculating Actual TX Data FIFO Usage 9.8.6Transmit Examples Data Passed to the TX Data FIFO 9.8.6.2TX Example Data Written to the Data Passed to the Memory Mapped TX Data FIFO Port 9.8.7Transmitter Errors 9.8.8Stopping and Starting the Transmitter 9.9RX Data Path Operation 9.9.1RX Slave PIO Operation Page 9.9.2RX Packet Format 9.9.3RX Status Format 9.9.4Stopping and Starting the Receiver 9.9.5Receiver Errors Chapter 10 Serial Management 10.1Functional Overview 10.2I2C/Microwire Master EEPROM Controller 10.2.1EEPROM Controller Operation 10.2.2I2C EEPROM 10.2.2.1I2C Protocol Overview 10.2.2.2I2C EEPROM Device Addressing 10.2.2.3I2C EEPROM Byte Read 10.2.2.4I2C EEPROM Sequential Byte Reads 10.2.2.5I2C EEPROM Byte Writes 10.2.3Microwire EEPROM 10.2.3.2ERASE (Erase Location) 10.2.3.3ERAL (Erase All) 10.2.3.4EWDS (Erase/Write Disable) 10.2.3.5EWEN (Erase/Write Enable) 10.2.3.6READ (Read Location) 10.2.3.7WRITE (Write Location) 10.2.3.8WRAL (Write All) 10.2.4EEPROM Loader Page 10.2.4.2EEPROM Valid Flag 10.2.4.3MAC Address 10.2.4.4Soft-Straps 10.2.4.5Register Data 10.2.4.6EEPROM Loader Finished Wait-State 10.2.4.7Reset Sequence and EEPROM Loader Chapter 11 IEEE 1588 Hardware Time Stamp Unit 11.1Functional Overview 11.1.1IEEE 11.1.2Block Diagram 11.2IEEE 1588 Time Stamp 11.2.1Capture Locking 11.2.2PTP Message Detection 11.3IEEE 1588 Clock 11.4IEEE 1588 Clock/Events 11.5IEEE 1588 GPIOs 11.6IEEE 1588 Interrupts 12.1General Purpose Timer 12.2Free-RunningClock Chapter 13 GPIO/LED Controller 13.1Functional Overview 13.2GPIO Operation 13.2.1GPIO IEEE 1588 Timestamping 13.2.2GPIO Interrupts 13.3LED Operation Page Chapter 14 Register Descriptions 14.1TX/RX FIFO Ports 14.1.1TX/RX Data FIFO’s 14.1.2TX/RX Status FIFO’s 14.1.3Direct FIFO Access Mode 14.2System Control and Status Registers Page Page Page 14.2.1Interrupts Page 14.2.1.2Interrupt Status Register (INT_STS) Page Page 14.2.1.3Interrupt Enable Register (INT_EN) Page 14.2.1.4FIFO Level Interrupt Register (FIFO_INT) 14.2.2Host MAC & FIFO’s Page 14.2.2.2Transmit Configuration Register (TX_CFG) 14.2.2.3Receive Datapath Control Register (RX_DP_CTRL) 14.2.2.4RX FIFO Information Register (RX_FIFO_INF) 14.2.2.5TX FIFO Information Register (TX_FIFO_INF) 14.2.2.6Host MAC RX Dropped Frames Counter Register (RX_DROP) 14.2.2.7Host MAC CSR Interface Command Register (MAC_CSR_CMD) 14.2.2.8Host MAC CSR Interface Data Register (MAC_CSR_DATA) 14.2.2.9Host MAC Automatic Flow Control Configuration Register (AFC_CFG) Page Page 14.2.3GPIO/LED Page 14.2.3.2General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) 14.2.3.4LED Configuration Register (LED_CFG) 14.2.4EEPROM Page Page 14.2.4.2EEPROM Data Register (E2P_DATA) 14.2.5IEEE Page Page Page Page Page Page Port x 1588 Source UUID Page Page Page Page 14.2.5.131588 Clock High-DWORDRegister (1588_CLOCK_HI) 14.2.5.141588 Clock Low-DWORDRegister (1588_CLOCK_LO) 14.2.5.151588 Clock Addend Register (1588_CLOCK_ADDEND) 14.2.5.161588 Clock Target High-DWORDRegister (1588_CLOCK_TARGET_HI) 14.2.5.171588 Clock Target Low-DWORDRegister (1588_CLOCK_TARGET_LO) Page Page 14.2.5.201588 Auxiliary MAC Address High-WORDRegister (1588_AUX_MAC_HI) 14.2.5.211588 Auxiliary MAC Address Low-DWORDRegister (1588_AUX_MAC_LO) 14.2.5.221588 Configuration Register (1588_CONFIG) Page Page Page 14.2.5.231588 Interrupt Status and Enable Register (1588_INT_STS_EN) Page 14.2.5.241588 Command Register (1588_CMD) 14.2.6Switch Fabric Page 14.2.6.2Port 2 Manual Flow Control Register (MANUAL_FC_2) Page 14.2.6.3Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) Page 14.2.6.4Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) 14.2.6.5Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) Page 14.2.6.6Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) 14.2.6.7Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) Page Page 14.2.7PHY Management Interface (PMI) 14.2.7.2PHY Management Interface Access Register (PMI_ACCESS) 14.2.8Virtual PHY 14.2.8.1Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) Page 14.2.8.2Virtual PHY Basic Status Register (VPHY_BASIC_STATUS) Page 14.2.8.3Virtual PHY Identification MSB Register (VPHY_ID_MSB) 14.2.8.4Virtual PHY Identification LSB Register (VPHY_ID_LSB) 14.2.8.5Virtual PHY Auto-NegotiationAdvertisement Register (VPHY_AN_ADV) Page Page Page 14.2.8.7Virtual PHY Auto-NegotiationExpansion Register (VPHY_AN_EXP) Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) Page 14.2.9Miscellaneous 14.2.9.2Byte Order Test Register (BYTE_TEST) 14.2.9.3Hardware Configuration Register (HW_CFG) Page 14.2.9.4Power Management Control Register (PMT_CTRL) Page 14.2.9.5General Purpose Timer Configuration Register (GPT_CFG) 14.2.9.6General Purpose Timer Count Register (GPT_CNT) 14.2.9.7Free Running 25MHz Counter Register (FREE_RUN) 14.2.9.8Reset Control Register (RESET_CTL) 14.3Host MAC Control and Status Registers 14.3.1Host MAC Control Register (HMAC_CR) Page Page 14.3.2Host MAC Address High Register (HMAC_ADDRH) 14.3.3Host MAC Address Low Register (HMAC_ADDRL) 14.3.4Host MAC Multicast Hash Table High Register (HMAC_HASHH) 14.3.5Host MAC Multicast Hash Table Low Register (HMAC_HASHL) 14.3.6Host MAC MII Access Register (HMAC_MII_ACC) 14.3.7Host MAC MII Data Register (HMAC_MII_DATA) 14.3.8Host MAC Flow Control Register (HMAC_FLOW) Page 14.3.9Host MAC VLAN1 Tag Register (HMAC_VLAN1) 14.3.10Host MAC VLAN2 Tag Register (HMAC_VLAN2) 14.3.11Host MAC Wake-upFrame Filter Register (HMAC_WUFF) 14.3.12Host MAC Wake-upControl and Status Register (HMAC_WUCSR) 14.4Ethernet PHY Control and Status Registers 14.4.1Virtual PHY Registers 14.4.2Port 1 & 2 PHY Registers Page 14.4.2.1Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) Page 14.4.2.2Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) Page 14.4.2.3Port x PHY Identification MSB Register (PHY_ID_MSB_x) 14.4.2.4Port x PHY Identification LSB Register (PHY_ID_LSB_x) 14.4.2.5Port x PHY Auto-NegotiationAdvertisement Register (PHY_AN_ADV_x) Page Page Page Page 14.4.2.7Port x PHY Auto-NegotiationExpansion Register (PHY_AN_EXP_x) 14.4.2.8Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) 14.4.2.9Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) Page Page Page 14.4.2.11Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) 14.4.2.12Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x) 14.5Switch Fabric Control and Status Registers Page Page Page Page Page Page Page Page Page Page 14.5.1General Switch CSRs 14.5.1.2Switch Reset Register (SW_RESET) 14.5.1.3Switch Global Interrupt Mask Register (SW_IMR) 14.5.1.4Switch Global Interrupt Pending Register (SW_IPR) 14.5.2Switch Port 0, Port 1, and Port 2 CSRs 14.5.2.2Port x MAC Receive Configuration Register (MAC_RX_CFG_x) 14.5.2.3Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) 14.5.2.4Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x) Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x) Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x) Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x) Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x) Page 14.5.2.10Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) 14.5.2.11Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x) 14.5.2.12Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x) 14.5.2.13Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x) 14.5.2.14Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) 14.5.2.15Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x) 14.5.2.16Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x) 14.5.2.17Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x) 14.5.2.18Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) 14.5.2.19Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x) Page 14.5.2.21Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x) 14.5.2.22Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) 14.5.2.23Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) 14.5.2.25Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) 14.5.2.26Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) 14.5.2.27Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x) 14.5.2.28Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x) Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x) Page Page 14.5.2.34Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) 14.5.2.35Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) 14.5.2.36Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) 14.5.2.37Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x) Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x) Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x) Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x) 14.5.2.43Port x MAC Interrupt Mask Register (MAC_IMR_x) 14.5.2.44Port x MAC Interrupt Pending Register (MAC_IPR_x) 14.5.3Switch Engine CSRs 14.5.3.2Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) 14.5.3.3Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) Page 14.5.3.4Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0) 14.5.3.5Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) Page 14.5.3.6Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) 14.5.3.7Switch Engine ALR Configuration Register (SWE_ALR_CFG) 14.5.3.8Switch Engine VLAN Command Register (SWE_VLAN_CMD) 14.5.3.9Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA) 14.5.3.10Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) 14.5.3.11Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) 14.5.3.12Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG) Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) Page Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG) Page Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG) 14.5.3.18Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN) 14.5.3.19Switch Engine Port State Register (SWE_PORT_STATE) 14.5.3.20Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE) 14.5.3.21Switch Engine Port Mirroring Register (SWE_PORT_MIRROR) 14.5.3.22Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) 14.5.3.23Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) 14.5.3.24Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER) Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) 14.5.3.26Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD) Page Page Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA) Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA) Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII) Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1) Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) Page Page Page Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII) Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1) Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2) 14.5.3.39Switch Engine Interrupt Mask Register (SWE_IMR) 14.5.3.40Switch Engine Interrupt Pending Register (SWE_IPR) Page 14.5.4Buffer Manager CSRs 14.5.4.2Buffer Manager Drop Level Register (BM_DROP_LVL) 14.5.4.3Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL) 14.5.4.4Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL) 14.5.4.5Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL) 14.5.4.6Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII) 14.5.4.7Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) 14.5.4.8Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2) 14.5.4.9Buffer Manager Reset Status Register (BM_RST_STS) Page Page Page 14.5.4.13Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) Page Page Page Page Page Page Page Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII) Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1) Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) Page Page Page 14.5.4.26Buffer Manager Interrupt Mask Register (BM_IMR) 14.5.4.27Buffer Manager Interrupt Pending Register (BM_IPR) Page Chapter 15 Operational Characteristics 15.1Absolute Maximum Ratings 15.2Operating Conditions 15.3Power Consumption 15.4DC Specifications 15.5AC Specifications 15.5.1Equivalent Test Load 15.5.2Reset and Configuration Strap Timing 15.5.3Power-OnConfiguration Strap Valid Timing 15.5.4PIO Read Cycle Timing 15.5.5PIO Burst Read Cycle Timing 15.5.6RX Data FIFO Direct PIO Read Cycle Timing 15.5.7RX Data FIFO Direct PIO Burst Read Cycle Timing 15.5.8PIO Write Cycle Timing 15.5.9TX Data FIFO Direct PIO Write Cycle Timing 15.5.10Microwire Timing 15.6Clock Circuit Chapter 16 Package Outlines 16.1128-VTQFPPackage Outline Page 16.2128-XVTQFPPackage Outline Page Chapter 17 Revision History