High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
5.2.3Ethernet PHY Interrupts
The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The
Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x). The source of a PHY interrupt can be determined and cleared via the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). The Port 1 and Port 2 PHYs are each capable of generating unique interrupts based on the following events:
ENERGYON Activated
Remote Fault Detected
Link Down (Link Status Negated)
Parallel Detection Fault
In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY interrupt event must be enabled in the corresponding Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY_INT1(Port 1 PHY) and/or PHY_INT2(Port 2 PHY) bits of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).
For additional details on the Ethernet PHY interrupts, refer to Section 7.2.8.1, "PHY Interrupts," on page 94.
5.2.4GPIO Interrupts
Each GPIO[11:0] of the LAN9312 is provided with its own interrupt. The
In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt must be enabled in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN), bit 12 (GPIO_EN) of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).
For additional details on the GPIO interrupts, refer to Section 13.2.2, "GPIO Interrupts," on page 163.
5.2.5Host MAC Interrupts
The
TX Stopped
RX Stopped
RX Dropped Frame Counter Halfway
TX IOC
RX DMA
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