High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
A POR reset typically takes approximately 23mS, plus additional time (91uS for I2C, 28uS for Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load (64KB for I2C, 2KB for Microwire) will complete in approximately 6.0 seconds for I2C EEPROM, and 80mS for Microwire EEPROM.
4.2.1.2nRST Pin Reset
Driving the nRST input pin low initiates a
A nRST pin reset typically takes approximately 760uS, plus additional time (91uS for I2C, 28uS for
Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load (64KB for I2C, 2KB for Microwire) will complete in approximately 6.0 seconds for I2C EEPROM, and 58mS for Microwire EEPROM.
Note: The nRST pin is
Please refer to Section Table 3.7, "Miscellaneous Pins," on page 33 for a description of the nRST pin.
4.2.2Multi-Module Resets
With the exception of the Hardware Configuration Register (HW_CFG), Power Management Control Register (PMT_CTRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal resources is forbidden while the READY bit is cleared. Writes to any address are invalid until the READY bit is set.
Note: The digital reset and soft reset do not reset register bits designated as NASR.
Note: The LAN9312 must be read at least once after a
4.2.2.1Digital Reset (DIGITAL_RST)
A digital reset is performed by setting the DIGITAL_RST bit of the Reset Control Register (RESET_CTL). A digital reset will reset all LAN9312
A digital reset typically takes approximately 760uS, plus additional time (91uS for I2C, 28uS for
Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load (64KB for I2C, 2KB for Microwire) will complete in approximately 6.0 seconds for I2C EEPROM, and 58mS for Microwire EEPROM.
Revision 1.4 | 38 | SMSC LAN9312 |
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