High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
| Table 4.2 |
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STRAP NAME |
| DESCRIPTION | PIN / DEFAULT | |
| VALUE | |||
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LED_en_strap[7:0] |
| LED Enable Straps: Configures the default value for the | LED_EN | |
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| LED_EN bits in the LED Configuration Register |
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| (LED_CFG). A high value configures the associated |
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| LED/GPIO pin as a LED. A low value configures the |
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| associated LED/GPIO pin as a GPIO. |
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| Note: | One pin configures the default for all 8 |
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| LED/GPIOs, but 8 separate bits are loaded by the |
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| EEPROM Loader, allowing individual control over |
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| each LED/GPIO. |
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LED_fun_strap[1:0] |
| LED Function Straps: Configures the default value for the | 00b | |
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| LED_FUN bits in the LED Configuration Register |
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| (LED_CFG). When configured low, the corresponding bit |
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| will be cleared. When configured high, the corresponding |
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| bit will be set. |
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auto_mdix_strap_1 |
| Port 1 | AUTO_MDIX_1 | |
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| value for the |
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| AMDIXCTL bit in the Port x PHY Special Control/Status |
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| (PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared. |
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| When configured low, |
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| configured high, |
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| Note: | If AMDIXCTL is set, this strap had no effect. |
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manual_mdix_strap_1 |
| Port 1 Manual MDIX Strap: Configures MDI(0) or MDIX(1) | 0b | |
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| for Port 1 when the auto_mdix_strap_1 is low and the |
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| AMDIXCTL bit of the Port x PHY Special Control/Status |
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| (PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared. |
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autoneg_strap_1 |
| Port 1 Auto Negotiation Enable Strap: Configures the | 1b | |
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| default value for the |
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| in the PHY_BASIC_CTRL_1 register (See |
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| Section 14.4.2.1). When configured low, |
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| disabled. When configured high, |
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| enabled. |
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| This strap also affects the default value of the following bits: |
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| PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the |
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| (bit 5) bits of the Port x PHY |
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| MODE[2:0] bits of the Port x PHY Special Modes Register |
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| Refer to the respective register definition sections for |
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| additional information. |
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SMSC LAN9312 | 41 | Revision 1.4 |
| DATASHEET |
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