High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
8.4.4PIO Reads
PIO reads can be used to access System CSR’s or RX Data and RX/TX Status FIFOs. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Read cycle begins when both nCS and nRD are asserted. Either or both of these control signals must
The endian select signal (END_SEL) has the same timing characteristics as the address lines.
Please refer to Section 15.5.4, "PIO Read Cycle Timing," on page 446 for the AC timing specifications for PIO read operations.
Note: Some registers have restrictions on the timing of
END_SEL |
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A[x:2] |
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nCS, nRD |
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D[31:0] (OUTPUT) |
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Figure 8.3 Functional Timing for PIO Read Operation
Revision 1.4 | 106 | SMSC LAN9312 |
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