High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.5.2.26Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x)

Register #:

Port0: 0452h

Size:

32 bits

 

Port1:

0852h

 

 

 

Port2:

0C52h

 

 

This register provides a counter of transmitted pause packets. The counter is cleared upon being read.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:0

TX Pause

RC

00000000h

 

Count of pause packets transmitted.

 

 

 

Note: This counter will stop at its maximum value of FFFF_FFFFh.

 

 

 

Minimum rollover time at 100Mbps is approximately 481 hours.

 

 

 

 

 

 

SMSC LAN9312

347

Revision 1.4 (08-19-08)

 

DATASHEET