High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.5.4Buffer Manager CSRs
This section details the Buffer Manager (BM) registers. These registers allow configuration and monitoring of the switch buffer levels and usage. A list of the general switch CSRs and their corresponding register numbers is included in Table 14.12.
14.5.4.1Buffer Manager Configuration Register (BM_CFG)
Register #: | 1C00h | Size: | 32 bits |
This register enables egress rate pacing and ingress rate discarding.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:7 | RESERVED | RO | - |
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6 | BM Counter Test | R/W | 0b |
| When this bit is set, Buffer Manager (BM) counters that normally clear to 0 |
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| when read, will be set to 7FFF_FFFC when read. |
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5 | Fixed Priority Queue Servicing | R/W | 0b |
| When set, output queues are serviced with a fixed priority ordering. When |
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| cleared, output queues are serviced with a weighted round robin ordering. |
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4:2 | Egress Rate Enable | R/W | 0b |
| When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch |
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| ports 2,1,0 respectively. |
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1 | Drop on Yellow | R/W | 0b |
| When this bit is set, packets that exceed the Ingress Committed Burst Size |
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| (colored Yellow) are subjected to random discard. |
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| Note: See Section 14.5.3.26, "Switch Engine Ingress Rate Command |
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| information on configuring the Ingress Committed Burst Size. |
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0 | Drop on Red | R/W | 0b |
| When this bit is set, packets that exceed the Ingress Excess Burst Size |
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| (colored Red) are discarded. |
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| Note: See Section 14.5.3.26, "Switch Engine Ingress Rate Command |
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| information on configuring the Ingress Excess Burst Size. |
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SMSC LAN9312 | 411 | Revision 1.4 |
| DATASHEET |
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