High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.5.2.23Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)Register #: | Port0: 0440h | Size: | 32 bits | |
| Port1: | 0840h |
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| Port2: | 0C40h |
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This read/write register configures the transmit packet parameters of the port.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:8 | RESERVED | RO | - |
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7 | MAC Counter Test | R/W | 0b |
| When set, TX and RX counters that normally clear to 0 when read, will be |
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| set to 7FFF_FFFCh when read with the exception of the Port x MAC |
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| Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x), Port x |
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| MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x), |
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| (MAC_RX_GOODPKTLEN_CNT_x) counters which will be set to |
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| 7FFF_FF80h. |
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6:2 | IFG Config | R/W | 10101b |
| These bits control the transmit |
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| IFG bit times = (IFG Config *4) + 12 |
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1 | TX Pad Enable | R/W | 1b |
| When set, packets shorter than 64 bytes are padded with zeros if needed |
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| and a FCS is appended. Packets that are 60 bytes or less will become 64 |
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| bytes. Packets that are 61, 62, and 63 bytes will become 65, 66, and 67 |
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| bytes respectively. |
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0 | TX Enable | R/W | 1b |
| When set, the transmit port is enabled. When cleared, the transmit port is |
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| disabled. |
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Revision 1.4 | 344 | SMSC LAN9312 |
| DATASHEET |
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