High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
Note 14.42 The reserved bits
Note 14.43 The default value of this field is the result of the
Note 14.44 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via the Reset Control Register (RESET_CTL) or Power Management Control Register (PMT_CTRL). The NASR designation is only applicable when the Reset (VPHY_RST) bit of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is set.
Note 14.45 The default value of this field is determined via the SQE_test_disable_strap_mii configuration strap. Refer to Section 4.2.4, "Configuration Straps," on page 40 for additional information.
Revision 1.4 | 258 | SMSC LAN9312 |
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