High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
BITS |
| DESCRIPTION | TYPE | DEFAULT |
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8:7 | RESERVED | RO | - | |
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6 | PME Buffer Type (PME_TYPE) | R/W | 0b | |
| When this bit is cleared, the PME pin functions as an | NASR |
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| use in a |
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| Note: | When PME is configured as an |
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| field of this register is ignored and the output is always active low. |
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| 0: PME pin |
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| 1: PME pin |
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5 | Wake On LAN Status (WOL_STS) | R/WC | 0b | |
| This bit indicates that a |
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| Host MAC. |
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| In order to clear this bit, it is required that the event in the Host MAC be |
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| cleared as well. The event sources are described in Section 4.3, "Power |
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4 | RESERVED | RO | - | |
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3 | PME Indication (PME_IND) | R/W | 0b | |
| The PME signal can be configured as a pulsed output or a static signal, |
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| which is asserted upon detection of a |
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| signal will pulse active for 50mS upon detection of a |
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| cleared, the PME signal is driven continuously upon detection of a |
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| event. |
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| 0: PME 50mS pulse on detection of event |
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| 1: PME driven continuously on detection of event |
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| The PME signal can be deactivated by clearing the WOL_STS bit or by |
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| clearing the appropriate enable. |
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2 | PME Polarity (PME_POL) | R/W | 0b | |
| This bit controls the polarity of the PME signal. When set, the PME output | NASR |
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| is an active high signal. When cleared, it is active low. |
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| Note: | When PME is configured as an |
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| ignored and the output is always active low. |
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| 0: PME active low |
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| 1: PME active high |
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1 | PME Enable (PME_EN) | R/W | 0b | |
| When set, this bit enables the external PME signal pin. When cleared, the |
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| external PME signal is disabled. |
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| Note: | This bit does not affect the PME_INT interrupt bit of the Interrupt |
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| 0: PME pin disabled |
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| 1: PME pin enabled |
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0 | Device Ready (READY) | RO | 0b | |
| When set, this bit indicates that the LAN9312 is ready to be accessed. Upon |
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| interrogate this field as an indication that the LAN9312 has stabilized and is |
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| fully active. |
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| This bit can cause an interrupt if enabled. |
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| Note: | With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and |
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| RESET_CTL registers, read access to any internal resources is |
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| forbidden while the READY bit is cleared. Writes to any address |
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| are invalid until this bit is set. |
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| Note: | This bit is identical to bit 27 of the Hardware Configuration Register |
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Revision 1.4 | 264 | SMSC LAN9312 |
| DATASHEET |
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