SMSC LAN9312 15.5.6RX Data FIFO Direct PIO Read Cycle Timing

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.5.6RX Data FIFO Direct PIO Read Cycle Timing

Please refer to Section 8.4.6, "RX Data FIFO Direct PIO Reads," on page 108 for a functional description of this mode.

FIFO_SEL

A[x:2], END_SEL

tcycle

tasu

tah

nCS, nRD

tcsl

tcsh

tcsdv

tdoh

tdoff

D[31:0]

tdon

Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing

Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcycle

Read Cycle Time

45

nS

tcsl

CS, nRD Assertion Time

32

nS

tcsh

nCS, nRD De-assertion Time

13

nS

tcsdv

nCS, nRD Valid to Data Valid

30

nS

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

0

nS

tah

Address, FIFO_SEL Hold Time

0

nS

tdon

Data Buffer Turn On Time

0

nS

tdoff

Data Buffer Turn Off Time

9

nS

tdoh

Data Output Hold Time

0

nS

Note: A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de- asserted in any order.

Revision 1.4 (08-19-08)	448	SMSC LAN9312
	DATASHEET