High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.2.4EEPROM
This section details the EEPROM related System CSR’s. These registers should only be used if an EEPROM has been connected to the LAN9312. Refer to chapter Section 10.2, "I2C/Microwire Master EEPROM Controller," on page 137 for additional information on the various modes (I2C and Microwire) of the EEPROM Controller (EPC).
14.2.4.1EEPROM Command Register (E2P_CMD)
Offset: | 1B4h | Size: | 32 bits |
This read/write register is used to control the read and write operations of the serial EEPROM.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31 | EEPROM Controller Busy (EPC_BUSY) | R/W | 0b |
| When a 1 is written into this bit, the operation specified in the | SC |
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| EPC_COMMAND field of this register is performed at the specified |
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| EEPROM address. This bit will remain set until the selected operation is |
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| complete. In the case of a read, this indicates that the Host can read valid |
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| data from the EEPROM Data Register (E2P_DATA). The E2P_CMD and |
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| E2P_DATA registers should not be modified until this bit is cleared. In the |
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| case where a write is attempted and an EEPROM is not present, the |
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| EPC_BUSY bit remains set until the EEPROM Controller Timeout |
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| (EPC_TIMEOUT) bit is set. At this time the EPC_BUSY bit is cleared. |
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| Note: EPC_BUSY is set immediately following |
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| DIGITAL_RST reset. This bit is also set following the settings of the |
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| SRST bit in the Hardware Configuration Register (HW_CFG). After |
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| the EEPROM Loader has finished loading, the EPC_BUSY bit is |
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| cleared. Refer to chapter Section 10.2.4, "EEPROM Loader," on |
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| page 149 for more information. |
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SMSC LAN9312 | 197 | Revision 1.4 |
| DATASHEET |
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