High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.5.1.3Switch Global Interrupt Mask Register (SW_IMR)Register #: | 0004h | Size: | 32 bits |
This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch related interrupts in the Switch Global Interrupt Pending Register (SW_IPR) may be masked via this register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will unmask the interrupt. When an unmasked switch fabric interrupt is generated in the Switch Global Interrupt Pending Register (SW_IPR), the interrupt will trigger the SWITCH_INT bit in the Interrupt Status Register (INT_STS). Refer to Chapter 5, "System Interrupts," on page 49 for more information.
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| DESCRIPTION | TYPE | DEFAULT |
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31:9 | RESERVED | RO | - | |
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8:7 | RESERVED | R/W | 11b | |
| Note: | These bits must be written as 11b |
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6 | Buffer Manager Interrupt Mask (BM) | R/W | 1b | |
| When set, prevents the generation of switch fabric interrupts due to the |
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| Buffer Manager via the Buffer Manager Interrupt Pending Register |
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| (BM_IPR). The status bits in the SW_IPR register are not affected. |
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5 | Switch Engine Interrupt Mask (SWE) | R/W | 1b | |
| When set, prevents the generation of switch fabric interrupts due to the |
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| Switch Engine via the Switch Engine Interrupt Pending Register (SWE_IPR). |
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| The status bits in the SW_IPR register are not affected. |
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4:3 | RESERVED | R/W | 11b | |
| Note: | These bits must be written as 11b |
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2 | Port 2 MAC Interrupt Mask (MAC_2) | R/W | 1b | |
| When set, prevents the generation of switch fabric interrupts due to the Port |
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| 2 MAC via the MAC_IPR_2 register (see Section 14.5.2.44, on page 365). |
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| The status bits in the SW_IPR register are not affected. |
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1 | Port 1 MAC Interrupt Mask (MAC_1) | R/W | 1b | |
| When set, prevents the generation of switch fabric interrupts due to the Port |
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| 1 MAC via the MAC_IPR_1 register (see Section 14.5.2.44, on page 365). |
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| The status bits in the SW_IPR register are not affected. |
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0 | Port 0 MAC Interrupt Mask (MAC_MII) | R/W | 1b | |
| When set, prevents the generation of switch fabric interrupts due to the Port |
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| 0 MAC via the MAC_IPR_MII register (see Section 14.5.2.44, on page 365). |
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| The status bits in the SW_IPR register are not affected. |
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Revision 1.4 | 320 | SMSC LAN9312 |
| DATASHEET |
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