High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

7.2.2100BASE-TX Receive

The 100BASE-TX receive data path is shown in Figure 7.3. Shaded blocks are those which are internal to the PHY. Each major block is explained in the following sections.

 

Internal

100M

 

 

 

 

 

MII Receive Clock

PLL

 

 

 

 

 

Port x

 

 

 

 

 

 

 

 

MAC

 

 

 

 

 

 

 

 

 

Internal

MII MAC

25MHz

4B/5B

25MHz by

Descrambler

MII 25MHz by 4 bits

Interface

by 4 bits

Decoder

5 bits

and SIPO

 

 

 

 

125 Mbps Serial

 

 

NRZI

 

 

MLT-3

 

 

DSP: Timing

 

 

NRZI

 

MLT-3

recovery, Equalizer

 

Converter

 

Converter

 

 

 

 

 

 

and BLW Correction

 

 

 

 

 

 

 

 

A/D

 

MLT-3

Magnetics

MLT-3

RJ45

MLT-3

CAT-5

 

Converter

 

 

 

 

 

 

 

 

6 bit Data

Figure 7.3 100BASE-TX Receive Data Path

7.2.2.1A/D Converter

The MLT-3 data from the cable is fed into the PHY on inputs RXPx and RXNx (where “x” is replaced with “1” for the Port 1 PHY, or “2” for the Port 2 PHY) via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quantizer, 6 digital bits are generated to represent each sample. The DSP adjusts the gain of the A/D Converter (ADC) according to the observed signal levels such that the full dynamic range of the ADC can be used.

7.2.2.2DSP: Equalizer, BLW Correction and Clock/Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel (magnetics, connectors, and CAT- 5 cable). The equalizer can restore the signal for any good-quality CAT-5 cable between 1m and 150m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal.

SMSC LAN9312

87

Revision 1.4 (08-19-08)

 

DATASHEET