High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
7.2.2100BASE-TX Receive
The
| Internal | 100M |
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MII Receive Clock | PLL |
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Port x |
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MAC |
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| Internal | MII MAC | 25MHz | 4B/5B | 25MHz by | Descrambler | ||
MII 25MHz by 4 bits | Interface | by 4 bits | Decoder | 5 bits | and SIPO | |||
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| 125 Mbps Serial |
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NRZI |
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| DSP: Timing |
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| recovery, Equalizer |
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Converter |
| Converter |
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| and BLW Correction |
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A/D |
| Magnetics | RJ45 |
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Converter |
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6 bit Data
Figure 7.3
7.2.2.1A/D Converter
The
7.2.2.2DSP: Equalizer, BLW Correction and Clock/Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel (magnetics, connectors, and CAT- 5 cable). The equalizer can restore the signal for any
If the DC content of the signal is such that the
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal.
SMSC LAN9312 | 87 | Revision 1.4 |
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