High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

3

Auto-Negotiation Ability

RO

1b

 

This bit indicates the status of the PHY’s auto-negotiation.

 

 

 

0: PHY is unable to perform auto-negotiation

 

 

 

1: PHY is able to perform auto-negotiation

 

 

 

 

 

 

2

Link Status

RO/LL

0b

 

This bit indicates the status of the link.

 

 

 

0: Link is down

 

 

 

1: Link is up

 

 

 

 

 

 

1

Jabber Detect

RO/LH

0b

 

This bit indicates the status of the jabber condition.

 

 

 

0: No jabber condition detected

 

 

 

1: Jabber condition detected

 

 

 

 

 

 

0

Extended Capability

RO

1b

 

This bit indicates whether extended register capability is supported.

 

 

 

0: Basic register set capabilities only

 

 

 

1: Extended register set capabilities

 

 

 

 

 

 

Note 14.52 The PHY supports 100BASE-TX (half and full duplex) and 10BASE-T (half and full duplex) only. All other modes will always return as 0 (unable to perform).

Revision 1.4 (08-19-08)

290

SMSC LAN9312

 

DATASHEET