High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.8.6Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY)

Offset:

1D4h

Size:

32 bits

Index (decimal):

5

 

 

This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto- Negotiation process with the Virtual PHY. Because the Virtual PHY does not physically connect to an actual link partner, the values in this register are emulated as described below.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:16

RESERVED

RO

-

 

(See Note 14.33)

 

 

 

 

 

 

15

Next Page

RO

0b

 

This bit indicates the emulated link partner PHY next page capability and is

 

Note 14.34

 

always 0.

 

 

 

0: Link partner PHY does not advertise next page capability

 

 

 

1: Link partner PHY advertises next page capability

 

 

 

 

 

 

14

Acknowledge

RO

1b

 

This bit indicates whether the link code word has been received from the

 

Note 14.34

 

partner and is always 1.

 

 

 

0: Link code word not yet received from partner

 

 

 

1: Link code word received from partner

 

 

 

 

 

 

13

Remote Fault

RO

0b

 

Since there is no physical link partner, this bit is not used and is always

 

Note 14.34

 

returned as 0.

 

 

 

 

 

 

12

RESERVED

RO

-

 

 

 

 

11

Asymmetric Pause

RO

Note 14.35

 

This bit indicates the emulated link partner PHY asymmetric pause

 

 

 

capability.

 

 

 

0: No Asymmetric PAUSE toward link partner

 

 

 

1: Asymmetric PAUSE toward link partner

 

 

 

 

 

 

10

Pause

RO

Note 14.35

 

This bit indicates the emulated link partner PHY symmetric pause capability.

 

 

 

0: No Symmetric PAUSE toward link partner

 

 

 

1: Symmetric PAUSE toward link partner

 

 

 

 

 

 

9

100BASE-T4

RO

0b

 

This bit indicates the emulated link partner PHY 100BASE-T4 capability.

 

Note 14.34

 

This bit is always 0.

 

 

 

0: 100BASE-T4 ability not supported

 

 

 

1: 100BASE-T4 ability supported

 

 

 

 

 

 

8

100BASE-X Full Duplex

RO

Note 14.36

 

This bit indicates the emulated link partner PHY 100BASE-X full duplex

 

 

 

capability.

 

 

 

0: 100BASE-X full duplex ability not supported

 

 

 

1: 100BASE-X full duplex ability supported

 

 

 

 

 

 

Revision 1.4 (08-19-08)

254

SMSC LAN9312

 

DATASHEET