High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.5.2.25Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x)

Register #:

Port0: 0451h

Size:

32 bits

 

Port1:

0851h

 

 

 

Port2:

0C51h

 

 

This register provides a counter deferred packets. The counter is cleared upon being read.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:0

TX Deferred

RC

00000000h

 

Count of packets that were available for transmission but were deferred on

 

 

 

the first transmit attempt due to network traffic (either on receive or prior

 

 

 

transmission). This counter is not incremented on collisions. This counter is

 

 

 

incremented only in half-duplex operation.

 

 

 

Note: This counter will stop at its maximum value of FFFF_FFFFh.

 

 

 

Minimum rollover time at 100Mbps is approximately 481 hours.

 

 

 

 

 

 

Revision 1.4 (08-19-08)

346

SMSC LAN9312

 

DATASHEET