High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
Top Level Interrupt Registers
(System CSRs)
INT_CFG
INT_STS
INT_EN
Bit 29 (1588_EVNT) | 1588 Time Stamp Interrupt Register | |
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of INT_STS register | 1588_INT_STS_EN | |
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| Switch Fabric Interrupt Registers | |
Bit 28 (SWITCH_INT) | SW_IMR | |
of INT_STS register | ||
| ||
| SW_IPR |
Buffer Manager Interrupt Registers
Bit 6 (BM) | BM_IMR | |
of SW_IPR register | ||
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| BM_IPR | |
| Switch Engine Interrupt Registers | |
Bit 5 (SWE) | SWE_IMR | |
of SW_IPR register | ||
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| SWE_IPR | |
| Port [2,1,0] MAC Interrupt Registers | |
Bits [2,1,0] (MAC_[2,1,MII]) | MAC_IMR_[2,1,MII] | |
of SW_IPR register | ||
| ||
| MAC_IPR_[2,1,MII] |
Port 2 PHY Interrupt Registers
Bit 27 (PHY_INT2) | PHY_INTERRUPT_SOURCE_2 | |
of INT_STS register | ||
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| PHY_INTERRUPT_MASK_2 | |
| Port 1 PHY Interrupt Registers | |
Bit 26 (PHY_INT1) | PHY_INTERRUPT_SOURCE_1 | |
of INT_STS register | ||
| ||
| PHY_INTERRUPT_MASK_1 |
Bit 17 (PME_INT)
Power Management Control Register
of INT_STS register
PMT_CTRL
Bit 12 (GPIO)
GPIO Interrupt Register
of INT_STS register
GPIO_INT_STS_EN
Figure 5.1 Functional Interrupt Register Hierarchy
Revision 1.4 | 50 | SMSC LAN9312 |
| DATASHEET |
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