SMSC LAN9312 15.5.5PIO Burst Read Cycle Timing

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.5.5PIO Burst Read Cycle Timing

Please refer to Section 8.4.5, "PIO Burst Reads," on page 107 for a functional description of this mode.

A[x:5], END_SEL

tacyc	tacyc			tacyc
A[4:2]
tasu				tah	tcsh
nCS, nRD
tcsdv	tadv	tadv	tadv		tdoff
tdon					tdoh
D[31:0]

Figure 15.5 PIO Burst Read Cycle Timing

Table 15.9 PIO Burst Read Cycle Timing Values

SYMBOL	DESCRIPTION	MIN	TYP	MAX	UNITS
tcsh	nCS, nRD De-assertion Time	13			nS
tcsdv	nCS, nRD Valid to Data Valid			30	nS
tacyc	Address Cycle Time	45			nS
tasu	Address Setup to nCS, nRD Valid	0			nS
tadv	Address Stable to Data Valid			40	nS
tah	Address Hold Time	0			nS
tdon	Data Buffer Turn On Time	0			nS
tdoff	Data Buffer Turn Off Time			9	nS
tdoh	Data Output Hold Time	0			nS

Note: A host PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. These signals may be asserted and de- asserted in any order.

Note: Fresh data is supplied each time A[2] toggles.

SMSC LAN9312	447	Revision 1.4 (08-19-08)
	DATASHEET