High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

10.2.2.3I2C EEPROM Byte Read

Following the device addressing, a data byte may be read from the EEPROM by outputting a start condition and control byte with a control code of 1010b, chip/block select bits as described in Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by

8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I2C master then sends a no-acknowledge, followed by a stop condition.

Figure 10.4 illustrates typical I2C EEPROM byte read for single and double byte addressing.

Control Byte

A

S

1

0

1

0

A

A

A

1

C

1

9

8

K

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Byte

A

D

D

D

D

D

D

D

D

 

 

 

 

 

A

 

P

C

7

6

5

4

3

2

1

0

 

C

 

K

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

Control Byte

 

 

 

A

 

 

 

Data Byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

1

0

1

0

0

0

0

1

D

D

D

D

D

D

D

D

 

A

 

P

C

C

7

6

5

4

3

2

1

0

 

C

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip / Block R/~W

Chip / Block R/~W

Select Bits

Select Bits

Single Byte Addressing Read

Double Byte Addressing Read

Figure 10.4 I2C EEPROM Byte Read

For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller Operation," on page 138.

10.2.2.4I2C EEPROM Sequential Byte Reads

Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting a start condition and control byte with a control code of 1010b, chip/block select bits as described in Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by

8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I2C master then

sends an acknowledge, and the EEPROM responds with the next 8-bits of data. This continues until the last desired byte is read, at which point the I2C master sends a no-acknowledge, followed by a stop condition.

Figure 10.4 illustrates typical I2C EEPROM sequential byte reads for single and double byte addressing.

Control Byte

A

S

1

0

1

0

A

A

A

1

C

1

9

8

K

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Byte

A D D D D D D D D A CK 7 6 5 4 3 2 1 0 CK

 

 

 

 

Data Byte

 

 

 

 

 

 

CK ...

 

 

 

Data Byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

6

 

5

 

4

 

3

 

2

 

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

C

P

D

 

D

 

D

 

D

 

D

 

D

 

D

 

D

 

A

D

D

D

D

D

D

D

D

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip / Block R/~W

Select Bits

Single Byte Addressing Sequential Reads

A

 

 

 

Control Byte

 

 

 

A

 

 

 

Data Byte

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

1

0

1

0

0

0

0

1

D

D

D

D

D

D

D

D

C

C

7

6

5

4

3

2

1

0

C

K

 

 

 

 

 

 

 

 

 

 

 

 

 

K

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Byte

 

 

 

 

 

 

CK

...

 

 

 

Data Byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

6

 

5

 

4

 

3

 

2

 

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

C

P

D

 

D

 

D

 

D

 

D

 

D

 

D

 

D

 

A

 

D

D

D

D

D

D

D

D

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip / Block R/~W

Select Bits

Double Byte Addressing Sequential Reads

Figure 10.5 I2C EEPROM Sequential Byte Reads

Revision 1.4 (08-19-08)

142

SMSC LAN9312

 

DATASHEET