High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.5.3.14Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA)

Register #:

1813h

Size:

32 bits

This register is used to read the DIFFSERV table.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:3

RESERVED

RO

-

 

 

 

 

2:0

DIFFSERV Priority

RO

000b

 

These bits specify the assigned receive priority for IP packets with a ToS/CS

 

 

 

field that matches this index.

 

 

 

 

 

 

SMSC LAN9312

381

Revision 1.4 (08-19-08)

 

DATASHEET