High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Data path operations for the supported endian configurations are illustrated in Figure 8.1, "Little Endian Byte Ordering" and Figure 8.2, "Big Endian Byte Ordering".

.

32-BIT LITTLE ENDIAN

(END_SEL = 0)

INTERNAL ORDER

 

MSB

 

 

 

 

 

LSB

31

24

23

16

15

8

7

0

 

3

 

2

 

1

 

0

3

 

 

2

 

1

 

0

31

24

23

16

15

8

7

0

HOST DATA BUS

Figure 8.1 Little Endian Byte Ordering

.

32-BIT BIG ENDIAN

(END_SEL = 1)

INTERNAL ORDER

31

MSB

 

 

 

 

 

LSB

24

23

16

15

8

7

0

 

3

 

2

 

1

 

0

0

 

 

1

 

2

 

3

31

24

23

16

15

8

7

0

HOST DATA BUS

Figure 8.2 Big Endian Byte Ordering

Revision 1.4 (08-19-08)

100

SMSC LAN9312

 

DATASHEET