High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
BITS |
| DESCRIPTION | TYPE | DEFAULT |
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5 | Lock Enable GPIO 8 (LOCK_GPIO_8) | R/W | 1b | |
| This bit enables/disables the GPIO 8 lock. This lock prevents a 1588 capture |
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| from overwriting the Clock value if the 1588_GPIO8 interrupt in the 1588 |
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| Interrupt Status and Enable Register (1588_INT_STS_EN) is already set |
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| due to a previous capture. |
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| 0: Disables GPIO 8 Lock |
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| 1: Enables GPIO 8 Lock |
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4:3 | GPIO 9 Clock Event Mode (GPIO_EVENT_9) | R/W | 00b | |
| These bits determine the output on GPIO 9 when a clock target compare |
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| event occurs. |
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| 00: 100ns pulse output |
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| 01: Toggle output |
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| 10: 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output |
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| 11: RESERVED |
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| Note: The 1588_GPIO_OE[9] bit in the General Purpose I/O |
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| Configuration Register (GPIO_CFG) must be set in order for the |
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| GPIO output to be controlled by the 1588 block. |
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| Note: | The polarity of the pulse or level is set by the |
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| GPIO_EVENT_POL_9 bit in the General Purpose I/O Configuration |
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| Register (GPIO_CFG). The GPIOBUF[9] bit still determines the |
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| GPIO buffer type. |
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2:1 | GPIO 8 Clock Event Mode (GPIO_EVENT_8) | R/W | 00b | |
| These bits determine the output on GPIO 8 when a clock target compare |
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| event occurs. |
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| 00: 100ns pulse output |
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| 01: Toggle output |
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| 10: 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output |
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| 11: RESERVED |
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| Note: The 1588_GPIO_OE[8] bit in the General Purpose I/O |
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| Configuration Register (GPIO_CFG) must be set in order for the |
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| GPIO output to be controlled by the 1588 block. |
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| Note: | The polarity of the pulse or level is set by the |
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| GPIO_EVENT_POL_8 bit in the General Purpose I/O Configuration |
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| Register (GPIO_CFG). The GPIOBUF[8] bit still determines the |
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| GPIO buffer type. |
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0 | Reload/Add (RELOAD_ADD) | R/W | 0b | |
| This bit determines the course of action when a clock target compare event |
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| occurs. When set, the 1588 Clock Target |
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| (1588_CLOCK_TARGET_HI) and 1588 Clock Target |
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| (1588_CLOCK_TARGET_LO) are loaded from the 1588 Clock Target |
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| Reload |
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| (1588_CLOCK_TARGET_RELOAD_LO) when a clock target compare event |
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| occurs. When low, the Clock Target Low and High Registers are |
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| incremented by the Clock Target Reload Low Register when a clock target |
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| compare event occurs. |
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| 0: Reload upon a clock target compare event |
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| 1: Increment upon a clock target compare event |
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SMSC LAN9312 | 225 | Revision 1.4 |
| DATASHEET |
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