High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

18

EEPROM Loader Address Overflow (LOADER_OVERFLOW)

RO

0b

 

This bit indicates that the EEPROM Loader tried to read past the end of the

 

 

 

EEPROM address space. This indicates misconfigured EEPROM data.

 

 

 

This bit is cleared when the EEPROM Loader is restarted with a RELOAD

 

 

 

command, Soft Reset(SRST), or a Digital Reset(DIGITAL_RST).

 

 

 

 

 

 

17

EEPROM Controller Timeout (EPC_TIMEOUT)

R/WC

0b

 

This bit is set when a timeout occurs, indicating the last operation was

 

 

 

unsuccessful. If an EEPROM ERASE, ERAL, WRITE or WRAL operation is

 

 

 

performed and no response is received from the EEPROM within 30mS, the

 

 

 

EEPROM controller will timeout and return to its idle state.

 

 

 

For the I2C mode, the bit is also set if the EEPROM fails to respond with

 

 

 

the appropriate ACKs, if the EEPROM slave device holds the clock low for

 

 

 

more than 30ms, or if an unsupported EPC_COMMAND is attempted.

 

 

 

This bit is cleared when written high.

 

 

 

Note: When in Microwire mode, if an EEPROM device is not connected,

 

 

 

an internal pull-down on the EEDI pin will keep the EEDI signal low

 

 

 

and allow timeouts to occur. If EEDI is pulled high externally, EPC

 

 

 

commands will not time out if an EEPROM device is not connected.

 

 

 

In this case the EPC_BUSY bit will be cleared as soon as the

 

 

 

command sequence is complete. It should also be noted that the

 

 

 

ERASE, ERAL, WRITE and WRAL commands are the only EPC

 

 

 

commands that will timeout if an EEPROM device is not present

 

 

 

AND the EEDI signal is pulled low.

 

 

 

 

 

 

16

Configuration Loaded (CFG_LOADED)

RO

0b

 

When set, this bit indicates that a valid EEPROM was found and the

 

 

 

EEPROM Loader completed normally. This bit is set upon a successful load.

 

 

 

It is cleared on power-up, pin and DIGITAL_RST resets, Soft Reset(SRST),

 

 

 

or at the start of a RELOAD.

 

 

 

This bit is cleared when written high.

 

 

 

 

 

 

15:0

EEPROM Controller Address (EPC_ADDRESS)

R/W

0000h

 

This field is used by the EEPROM Controller to address a specific memory

 

 

 

location in the serial EEPROM. This address must be byte aligned.

 

 

 

 

 

 

SMSC LAN9312

199

Revision 1.4 (08-19-08)

 

DATASHEET