High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.5.181588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)

Offset:

184h

Size:

32 bits

This read/write register combined with 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO) form the 64-bit 1588 Clock Target Reload value. The 1588 Clock Target Reload is the value that is reloaded to the 1588 Clock Compare value when a clock compare event occurs and the Reload/Add (RELOAD_ADD) bit of the 1588 Configuration Register (1588_CONFIG) is set. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:0

Clock Target Reload High (CLOCK_TARGET_RELOAD_HI)

R/W

00000000h

 

This field contains the high 32-bits of the 64-bit 1588 Clock Target Reload

 

 

 

value that is reloaded to the 1588 Clock Compare value.

 

 

 

 

 

 

Note: Both this register and the 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO) must be written for either to be affected.

Revision 1.4 (08-19-08)

218

SMSC LAN9312

 

DATASHEET