SMSC LAN9312 15.5.7RX Data FIFO Direct PIO Burst Read Cycle Timing

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.5.7RX Data FIFO Direct PIO Burst Read Cycle Timing

Please refer to Section 8.4.7, "RX Data FIFO Direct PIO Burst Reads," on page 109 for a functional description of this mode.

FIFO_SEL

END_SEL

A[2]

tacyc

tacyc

tacyc

tah

nCS, nRD

tasu

tcsh

tcsdv

tadv

tadv

tadv

tdoff

D[31:0]

tdon

tdoh

Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing

Table 15.11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcsh

nCS, nRD De-assertion Time

13

nS

tcsdv

nCS, nRD Valid to Data Valid

30

nS

tacyc

Address Cycle Time

45

nS

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

0

nS

tadv

Address Stable to Data Valid

40

nS

tah

Address, FIFO_SEL Hold Time

0

nS

tdon

Data Buffer Turn On Time

0

nS

tdoff

Data Buffer Turn Off Time

9

nS

tdoh

Data Output Hold Time

0

nS

Note: A RX Data FIFO direct PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.

Note: Fresh data is supplied each time A[2] toggles.

SMSC LAN9312	449	Revision 1.4 (08-19-08)
	DATASHEET