High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

„16-Byte “Buffer End Alignment”

Figure 9.5 illustrates the TX command structure for this example, and also shows how data is passed to the TX Data FIFO.

 

Data Written to the

 

 

Memory Mapped

 

 

TX Data FIFO Port

 

TX Command 'A'

31

0

TX Command 'A'

 

Buffer End Alignment = 1

 

 

 

Data Start Offset = 7

TX Command 'B'

 

First Segment = 1

 

 

 

Last Segment = 0

7-Byte Data Start Offset

 

Buffer Size = 79

 

 

 

TX Command 'B'

 

 

Packet Length = 111

 

 

79-Byte Payload

 

10-Byte

 

End Padding

31

0

TX Command 'A'

TX Command 'A'

Buffer End Alignment = 1

 

Data Start Offset = 0

TX Command 'B'

First Segment = 0

 

Last Segment = 0

 

Buffer Size = 15

15-Byte Payload

TX Command 'B'

1B

Packet Length = 111

31

0

TX Command 'A'

10-Byte

TX Command 'A'

Buffer End Alignment = 1

End Offset Padding

Data Start Offset = 10

TX Command 'B'

First Segment = 0

 

Last Segment = 1

10-Byte

Buffer Size = 17

Data Start Offset

 

TX Command 'B'

 

Packet Length = 111

 

Data Passed to theTX Data FIFO

TX Command 'A'

TX Command 'B'

79-Byte Payload

TX Command 'A'

15-Byte Payload

TX Command 'A'

17-Byte Payload

NOTE: Extra bytes between buffers are not transmitted

17-Byte Payload Data

5-Byte End Padding

Figure 9.5 TX Example 1

SMSC LAN9312

129

Revision 1.4 (08-19-08)

 

DATASHEET