High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.1.3Interrupt Enable Register (INT_EN)

Offset:

05Ch

Size:

32 bits

This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of SW_INT_EN). For descriptions of each interrupt, refer to the Interrupt Status Register (INT_STS) bits, which mimic the layout of this register.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31

Software Interrupt Enable (SW_INT_EN)

R/W

0b

 

 

 

 

30

Device Ready Enable (READY_EN)

R/W

0b

 

 

 

 

29

1588 Interrupt Event Enable (1588_EVNT_EN)

R/W

0b

 

 

 

 

28

Switch Engine Interrupt Event Enable (SWITCH_INT_EN)

R/W

0b

 

 

 

 

27

Port 2 PHY Interrupt Event Enable (PHY_INT2_EN)

R/W

0b

 

 

 

 

26

Port 1 PHY Interrupt Event Enable (PHY_INT1_EN)

R/W

0b

 

 

 

 

25

TX Stopped Interrupt Enable (TXSTOP_INT_EN)

R/W

0b

 

 

 

 

24

RX Stopped Interrupt Enable (RXSTOP_INT_EN)

R/W

0b

 

 

 

 

23

RX Dropped Frame Counter Halfway Interrupt Enable

R/W

0b

 

(RXDFH_INT_EN)

 

 

 

 

 

 

22

RESERVED

RO

-

 

 

 

 

21

TX IOC Interrupt Enable (TIOC_INT_EN)

R/W

0b

 

 

 

 

20

RX DMA Interrupt Enable (RXD_INT_EN)

R/W

0b

 

 

 

 

19

GP Timer Interrupt Enable (GPT_INT_EN)

R/W

0b

 

 

 

 

18

RESERVED

RO

-

 

 

 

 

17

Power Management Event Interrupt Enable (PME_INT_EN)

R/W

0b

 

 

 

 

16

TX Status FIFO Overflow Interrupt Enable (TXSO_EN)

R/W

0b

 

 

 

 

15

Receive Watchdog Time-out Interrupt Enable (RWT_INT_EN)

R/W

0b

 

 

 

 

14

Receiver Error Interrupt Enable (RXE_INT_EN)

R/W

0b

 

 

 

 

13

Transmitter Error Interrupt Enable (TXE_INT_EN)

R/W

0b

 

 

 

 

12

GPIO Interrupt Event Enable (GPIO_EN)

R/W

0b

 

 

 

 

11

RESERVED - This bit must be written with 0b for proper operation.

R/W

0b

 

 

 

 

10

TX Data FIFO Overrun Interrupt Enable (TDFO_EN)

R/W

0b

 

 

 

 

9

TX Data FIFO Available Interrupt Enable (TDFA_EN)

R/W

0b

 

 

 

 

8

TX Status FIFO Full Interrupt Enable (TSFF_EN)

R/W

0b

 

 

 

 

7

TX Status FIFO Level Interrupt Enable (TSFL_EN)

R/W

0b

 

 

 

 

6

RX Dropped Frame Interrupt Enable (RXDF_INT_EN)

R/W

0b

 

 

 

 

SMSC LAN9312

177

Revision 1.4 (08-19-08)

 

DATASHEET