High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.4.2.12Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)

Index (decimal): 30

Size:

16 bits

This read/write register is used to enable or mask the various Port x PHY interrupts and is used in conjunction with the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

15:8

RESERVED

RO

-

 

 

 

 

7

INT7_MASK

R/W

0b

 

This interrupt mask bit enables/masks the ENERGYON interrupt.

 

 

 

0: Interrupt source is masked

 

 

 

1: Interrupt source is enabled

 

 

 

 

 

 

6

INT6_MASK

R/W

0b

 

This interrupt mask bit enables/masks the Auto-Negotiation interrupt.

 

 

 

0: Interrupt source is masked

 

 

 

1: Interrupt source is enabled

 

 

 

 

 

 

5

INT5_MASK

R/W

0b

 

This interrupt mask bit enables/masks the remote fault interrupt.

 

 

 

0: Interrupt source is masked

 

 

 

1: Interrupt source is enabled

 

 

 

 

 

 

4

INT4_MASK

R/W

0b

 

This interrupt mask bit enables/masks the Link Down (link status negated)

 

 

 

interrupt.

 

 

 

0: Interrupt source is masked

 

 

 

1: Interrupt source is enabled

 

 

 

 

 

 

3

INT3_MASK

R/W

0b

 

This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge

 

 

 

interrupt.

 

 

 

0: Interrupt source is masked

 

 

 

1: Interrupt source is enabled

 

 

 

 

 

 

2

INT2_MASK

R/W

0b

 

This interrupt mask bit enables/masks the Parallel Detection fault interrupt.

 

 

 

0: Interrupt source is masked

 

 

 

1: Interrupt source is enabled

 

 

 

 

 

 

1

INT1_MASK

R/W

0b

 

This interrupt mask bit enables/masks the Auto-Negotiation page received

 

 

 

interrupt.

 

 

 

0: Interrupt source is masked

 

 

 

1: Interrupt source is enabled

 

 

 

 

 

 

0

RESERVED

RO

-

 

 

 

 

SMSC LAN9312

305

Revision 1.4 (08-19-08)

 

DATASHEET