High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.4.2.12Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)Index (decimal): 30 | Size: | 16 bits |
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in conjunction with the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
BITS | DESCRIPTION | TYPE | DEFAULT |
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15:8 | RESERVED | RO | - |
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7 | INT7_MASK | R/W | 0b |
| This interrupt mask bit enables/masks the ENERGYON interrupt. |
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| 0: Interrupt source is masked |
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| 1: Interrupt source is enabled |
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6 | INT6_MASK | R/W | 0b |
| This interrupt mask bit enables/masks the |
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| 0: Interrupt source is masked |
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| 1: Interrupt source is enabled |
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5 | INT5_MASK | R/W | 0b |
| This interrupt mask bit enables/masks the remote fault interrupt. |
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| 0: Interrupt source is masked |
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| 1: Interrupt source is enabled |
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4 | INT4_MASK | R/W | 0b |
| This interrupt mask bit enables/masks the Link Down (link status negated) |
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| interrupt. |
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| 0: Interrupt source is masked |
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| 1: Interrupt source is enabled |
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3 | INT3_MASK | R/W | 0b |
| This interrupt mask bit enables/masks the |
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| interrupt. |
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| 0: Interrupt source is masked |
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| 1: Interrupt source is enabled |
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2 | INT2_MASK | R/W | 0b |
| This interrupt mask bit enables/masks the Parallel Detection fault interrupt. |
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| 0: Interrupt source is masked |
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| 1: Interrupt source is enabled |
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1 | INT1_MASK | R/W | 0b |
| This interrupt mask bit enables/masks the |
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| interrupt. |
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| 0: Interrupt source is masked |
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| 1: Interrupt source is enabled |
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0 | RESERVED | RO | - |
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SMSC LAN9312 | 305 | Revision 1.4 |
| DATASHEET |
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