High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
BITS | DESCRIPTION | TYPE | DEFAULT |
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19:16 | TX FIFO Size (TX_FIF_SZ) | R/W | 5h |
| This field sets the size of the TX FIFOs in 1KB values to a maximum of |
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| 14KB. The TX Status FIFO consumes 512 bytes of the space allocated by |
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| TX_FIF_SIZ, and the TX Data FIFO consumes the remaining space |
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| specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2KB (TX |
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| Data FIFO and Status FIFO combined). The TX Data FIFO is used for both |
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| TX data and TX commands. |
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| The RX Status and Data FIFOs consume the remaining space, which is |
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| equal to 16KB minus TX_FIF_SIZ. See section Section 9.7.3, "FIFO |
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| Memory Allocation Configuration," on page 121 for more information. |
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15:14 | RESERVED | RO | - |
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13:12 | RESERVED - This field must be written with 00b for proper operation. | R/W | 00b |
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11:1 | RESERVED | RO | - |
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0 | Soft Reset (SRST) | R/W | 0b |
| Writing 1 generates a software initiated reset to the Host Bus Interface, the | SC |
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| Host MAC, and System CSR’s below address 100h. The System CSR’s are |
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| all reset except for any NASR bits. Soft reset also clears any TX or RX |
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| errors in the Host MAC transmitter and receiver (TXE/RXE). This bit is self- |
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| clearing. In order to reset all values, the Reset Control Register |
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| (RESET_CTL) must be used. |
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| Note: This bit will read high during assertion of DIGITAL_RST in the |
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| Reset Control Register (RESET_CTL). The LAN9312 must always |
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| be read at least once after |
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| operations function correctly. |
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Note 14.47 The default value of this field is determined by the configuration strap auto_mdix_strap_2. See Section 4.2.4, "Configuration Straps," on page 40 for more information.
Note 14.48 The default value of this field is determined by the configuration strap auto_mdix_strap_1. See Section 4.2.4, "Configuration Straps," on page 40 for more information.
Revision 1.4 | 262 | SMSC LAN9312 |
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