High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
9.2Flow Control
The Host MAC supports full-duplex flow control using the pause operation and control frame. Half- duplex flow control using back pressure is also supported. The Host MAC flow control is configured via the memory mapped Host MAC Automatic Flow Control Configuration Register (AFC_CFG) located in the System CSR space and the Host MAC Flow Control Register (HMAC_FLOW) located in the Host MAC CSR space.
Note: The Host MAC controls the flow between the switch fabric and the Host MAC, not the network flow control. The switch fabric handles the network flow control independently.
9.2.1Full-Duplex Flow Control
In full-duplex mode, flow control is achieved via the pause operation and the transmission of control frames. The pause operation inhibits transmission of data frames for a specified period of time. A pause operation consists of a frame containing the globally assigned multicast address (01-80-C2-00- 00-01), the PAUSE opcode, and a parameter indicating the quantum of slot time (512 bit times) to inhibit data transmissions. The PAUSE parameter may range from 0 to 65,535 slot times. The Host MAC logic, upon receiving a frame with the reserved multicast address and PAUSE opcode, inhibits data frame transmissions for the length of time indicated. If a pause request is received while a transmission is in progress, the pause will take effect after the transmission is complete. Control frames are received, processed by the Host MAC, and passed on.
The Host MAC also has the capability of transmitting control frames (pause command) via hardware and software control. The software driver requests the Host MAC to transmit a control frame and gives the value of the PAUSE time to be used in the control frame. The Host MAC function constructs a control frame by setting the appropriate values in the corresponding fields (as defined in the 802.3 specification) and transmits the frame to the internal MII interface. The transmission of the control frame is not affected by the current state of the Pause timer value that may be set due to a recently received control frame.
9.2.2Half-Duplex Flow Control (Backpressure)
In half-duplex mode, back pressure is used for flow control. Whenever the receive buffer/FIFO becomes full or crosses a certain threshold level, the Host MAC starts sending a jam signal. The Host MAC transmit logic enters a state at the end of current transmission (if any), where it waits for the beginning of a received frame. Once a new frame starts, the Host MAC starts sending the jam signal, which will result in a collision. After sensing the collision, the remote station will back off its transmission. The Host MAC continues sending the jam to make other stations defer transmission. The Host MAC only generates this collision-based back pressure when it receives a new frame, in order to avoid any late collisions.
9.3Virtual Local Area Network (VLAN) Support
Virtual Local Area Networks (VLANs), as defined within the IEEE 802.3 standard, provide network administrators a means of grouping nodes within a larger network into broadcast domains. To implement a VLAN, four extra bytes are added to the basic Ethernet packet. As shown in Figure 9.1, the four bytes are inserted after the Source Address Field and before the Type/Length field. The first two bytes of the VLAN tag identify the tag, and by convention are set to the value 0x8100. The last two bytes identify the specific VLAN associated with the packet and provide a priority field.
The LAN9312 supports VLAN-tagged packets and provides two Host MAC registers, Host MAC VLAN1 Tag Register (HMAC_VLAN1) and Host MAC VLAN2 Tag Register (HMAC_VLAN2), which are used to identify VLAN-tagged packets. The HMAC_VLAN1 register is used to specify the VLAN1 tag which will increase the legal frame length from 1518 to 1522 bytes. The HMAC_VLAN2 register is used to specify the VLAN2 tag which will increase the legal frame length from 1518 to 1538 bytes. If a packet arrives bearing either of these tags in the two bytes succeeding the Source Address field, the controller will recognize the packet as a VLAN-tagged packet, allowing the packet to be received and processed by the host software. If both VLAN1 and VLAN2 tag Identifiers are used, each should be unique. If
