SMSC LAN9312 15.5.10Microwire Timing

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.5.10Microwire Timing

This section specifies the Microwire EEPROM interface timing requirements. Please refer to Section 10.2.3, "Microwire EEPROM," on page 144 for a functional description of this serial interface.

				tcsl
	EECS
	tckcyc		tcklcsl
	tcshckh tckh tckl
	EECLK
	tdvckh tckhdis		tckldis
	EEDO
	tdsckh	tdhckh
	EEDI
	tcshdv		tdhcsl
EEDI (VERIFY)
	Figure 15.10 Microwire Timing
	Table 15.14 Microwire Timing Values
SYMBOL	DESCRIPTION	MIN	TYP	MAX	UNITS
tckcyc	EECLK cycle time	1110		1130	nS
tckh	EECLK high time	550		570	nS
tckl	EECLK low time	550		570	nS
tcshckh	EECS high before rising edge of EECLK	1070			nS
tcklcsl	EECLK falling edge to EECS low	30			nS
tdvckh	EEDO valid before rising edge of EECLK	550			nS
tckhdis	EEDO disable after rising edge of EECLK	550			nS
tdsckh	EEDI setup to rising edge of EECLK	90			nS
tdhckh	EEDI hold after rising edge of EECLK	0			nS
tckldis	EECLK low to EEDO data disable	580			nS
tcshdv	EEDI valid after EECS high (VERIFY)			600	nS
tdhcsl	EEDI hold after EECS low (VERIFY)	0			nS
tcsl	EECS low	1070			nS

Revision 1.4 (08-19-08)	452	SMSC LAN9312
	DATASHEET