High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.5.2Switch Port 0, Port 1, and Port 2 CSRs

This section details the switch Port 0(Host MAC), Port 1, and Port 2 CSRs. Each port provides a functionally identical set of registers which allow for the configuration of port settings, interrupts, and the monitoring of the various packet counters.

Because the Port 0, Port 1, and Port 2 CSRs are functionally identical, their register descriptions have been consolidated. A lowercase “x” has been appended to the end of each switch port register name in this section, where “x” should be replaced with “MII”, “1”, or “2” for the Port 0, Port 1, or Port 2 registers respectively. A list of the Switch Port 0, Port 1, and Port 2 registers and their corresponding register numbers is included in Table 14.12.

14.5.2.1Port x MAC Version ID Register (MAC_VER_ID_x)

Register #:

Port0: 0400h

Size:

32 bits

 

Port1:

0800h

 

 

 

Port2:

0C00h

 

 

This read-only register contains switch device ID information, including the device type, chip version and revision codes.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:12

RESERVED

RO

-

 

 

 

 

11:8

Device Type Code (DEVICE_TYPE)

RO

5h

 

 

 

 

7:4

Chip Version Code (CHIP_VERSION)

RO

8h

 

 

 

 

3:0

Revision Code (REVISION)

RO

3h

 

 

 

 

Revision 1.4 (08-19-08)

322

SMSC LAN9312

 

DATASHEET