High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

4

RX Status FIFO Full Interrupt (RSFF)

R/WC

0b

 

This interrupt is generated when the RX Status FIFO is full.

 

 

 

 

 

 

3

RX Status FIFO Level Interrupt (RSFL)

R/WC

0b

 

This interrupt is generated when the RX Status FIFO reaches the

 

 

 

programmed level in the RX Status Level field of the FIFO Level Interrupt

 

 

 

Register (FIFO_INT).

 

 

 

 

 

 

2:0

RESERVED

RO

-

 

 

 

 

Revision 1.4 (08-19-08)

176

SMSC LAN9312

 

DATASHEET