High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.5.2.2Port x MAC Receive Configuration Register (MAC_RX_CFG_x)Register #: | Port0: 0401h | Size: | 32 bits | |
| Port1: | 0801h |
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| Port2: | 0C01h |
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This read/write register configures the packet type passing parameters of the port.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:8 | RESERVED | RO | - |
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7 | RESERVED | R/W | 0b |
| Note: This bit must always be written as 0. |
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6 | RESERVED | RO | - |
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5 | Enable Receive Own Transmit | R/W | 0b |
| When set, the switch port will receive its own transmission if it is looped back |
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| from the PHY. Normally, this function is only used in Half Duplex PHY |
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| loopback. |
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4 | RESERVED | RO | - |
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3 | Jumbo2K | R/W | 0b |
| When set, the maximum packet size accepted is 2048 bytes. Statistics |
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| boundaries are also adjusted. |
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2 | RESERVED | RO | - |
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1 | Reject MAC Types | R/W | 1b |
| When set, MAC control frames (packets with a type field of 8808h) are |
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| filtered. When cleared, MAC Control frames, other than MAC Control Pause |
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| frames, are sent to the forwarding process. MAC Control Pause frames are |
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| always consumed by the switch. |
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0 | RX Enable | R/W | 1b |
| When set, the receive port is enabled. When cleared, the receive port is |
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| disabled. |
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SMSC LAN9312 | 323 | Revision 1.4 |
| DATASHEET |
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