High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers (continued)
INDEX # | SYMBOL | REGISTER NAME |
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17 | PHY_MODE_CONTROL_STATUS_x | Port x PHY Mode Control/Status Register, Section 14.4.2.8 |
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18 | PHY_SPECIAL_MODES_x | Port x PHY Special Modes Register, Section 14.4.2.9 |
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27 | PHY_SPECIAL_CONTROL_STAT_IND_x | Port x PHY Special Control/Status Indication Register, |
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29 | PHY_INTERRUPT_SOURCE_x | Port x PHY Interrupt Source Flags Register, Section 14.4.2.11 |
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30 | PHY_INTERRUPT_MASK_x | Port x PHY Interrupt Mask Register, Section 14.4.2.12 |
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31 | PHY_SPECIAL_CONTROL_STATUS_x | Port x PHY Special Control/Status Register, Section 14.4.2.13 |
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Revision 1.4 | 286 | SMSC LAN9312 |
| DATASHEET |
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