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Motorola MCF5281 User Manual
816 pages 9.41 Mb
5 Chapter 1 OverviewChapter 2 ColdFire Core 6 Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)7 Chapter 4 CacheChapter 5 Static RAM (SRAM) Chapter 6 ColdFire Flash Module (CFM) 8 Chapter 7 Power ManagementChapter 8 System Control Module (SCM) 9 Chapter 9 Clock ModuleChapter 10 Interrupt Controller Modules 11 Chapter 15 Synchronous DRAM Controller ModuleChapter 16 DMA Controller Module 12 Chapter 17 Fast Ethernet Controller (FEC)13 Chapter 18 Watchdog Timer ModuleChapter 19 Programmable Interrupt Timer Modules (PIT0PIT3) Chapter 20 General Purpose Timer Modules (GPTA and GPTB) 15 Chapter 21 DMA Timers (DTIM0DTIM3)Chapter 22 Queued Serial Peripheral Interface (QSPI) Module 16 Chapter 23 UART ModulesChapter 24 I2C Interface 17 Chapter 25 FlexCAN18 Chapter 26 General Purpose I/O ModuleChapter 27 Queued Analog-to-Digital Converter (QADC) 20 Chapter 28 Reset Controller ModuleChapter 29 Debug Support 21 Chapter 30 Chip Configuration Module (CCM)Chapter 31 IEEE 1149.1 Test Access Port (JTAG) 22 Chapter 32 Mechanical DataChapter 33 Electrical Characteristics Appendix A Register Memory Map 43 About This Book57 Chapter 1 Overview1.1 MCF5282 Key Features 71 1.2 MCF5282-Specific Features1.2.1 Fast Ethernet Controller (FEC) 1.2.2 FlexCAN 1.2.3 I2C Bus 1.2.4 Queued Serial Peripheral Interface (QSPI) 1.2.5 Queued Analog-to-Digital Converter (QADC)MOTOROLA Chapter2. ColdFire Core 2-1 73 Chapter 2 ColdFire Core101 BITREV Bit Reverse Register BITREV102 BYTEREV Byte Reverse Register BYTEREV103 FF1 Find First One in Register FF1104 STRLDSR Store/Load Status Register STRLDSR(Supported Starting with ISA A+) 105 Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)107 118 125 Chapter 4 Cache137 Chapter 5 Static RAM (SRAM)5.1 SRAM Features 5.2 SRAM Operation 5.3 SRAM Programming Model 143 Chapter 6 ColdFire Flash Module (CFM)169 Chapter 7 Power Management7.1 Features 7.2 Memory Map and Registers7.2.1 Programming Model 170 7.2.2 Memory Map7.2.3 Register Descriptions7.2.3.1 Low-Power Interrupt Control Register (LPICR)7-4 MCF5282 Users Manual MOTOROLA Memory Map and Registers 172 7.2.3.2 Low-Power Control Register (LPCR)The LPCR controls chip operation and module operation during low-power modes.Table7-3. XLPM_IPL Settings Figure 7-2. Low-Power Control Register (LPCR) Table7-4. LPCR Field Descriptions 173 7.3 Functional Description187 Chapter 8 System Control Module (SCM)207 Chapter 9 Clock Module229 Chapter 10 Interrupt Controller Modules247 Chapter 11 Edge Port Module (EPORT)255 Chapter 12 Chip Select Module12.1 Overview 12.2 Chip Select Module Signals 257 12.3 Chip Select Operation12.3.1 General Chip Select Operation 259 12.4 Chip Select RegistersTable12-5 shows the chip select register memory map. Reading reserved locations returns zeros. Table 12-4. D[19:18] External Boot Chip Select Configuration Table12 -5. Chip Select Registers12-6 MCF5282 Users Manual MOTOROLA Chip Select Registers 260 12.4.1 Chip Select Module RegistersFigure 12-2. Chip Select Address Registers (CSARn) 12.4.1.1 Chip Select Address Registers (CSAR0CSAR6)The CSARs, Figure 12-2, specify the chip select base addresses. Table12-6 describes CSAR[BA].Table12-5. Chip Select Registers (continu ed)MOTOROLA Chapter12. Chip Select Module 12-7 261 12.4.1.2 Chip Select Mask Registers (CSMR0CSMR6)Table12-7 describes CSMR fields.Table 12-6. CSARn Field Description Figure 12-3. Chip Select Mask Registers (CSMRn) Tabl e 12- 7. CS MRn Field Descriptions12-8 MCF5282 Users Manual MOTOROLA Chip Select Registers 262 12.4.1.3 Chip Select Control Registers (CSCR0CSCR6)Figure 12-4. Chip Select Control Registers (CSCRn) Table12-8 describes CSCRn fields. 265 Chapter 13 External Interface Module (EIM)281 Chapter 14 Signal Descriptions315 Chapter 15 Synchronous DRAM Controller Module15.1 Overview 317 15.2 SDRAM Controller Operation15-4 MCF5282 Users Manual MOTOROLA SDRAM Controller Operation 318 15.2.1 DRAM Controller SignalsTable15-2 describes the behavior of DRAM signals in synchronous mode. The DRAM controller registers memory map is shown in Table15-3. 15.2.2 Memory Map for SDRAMC RegistersTable15-2. Synchronous DRAM Signal Connections Table15-3. DRAM Controller RegistersMOTOROLA Chapter15. Synchronous DRAM Controller Module 15-5 319 15.2.2.1 DRAM Control Register (DCR)The DCR, shown in Figure 15-2, controls refresh logic. Table15-4 describes DCR fields.Figure 15-2. DRAM Control Register (DCR) Table15-4. DCR Field Descriptions15-6 MCF5282 Users Manual MOTOROLA SDRAM Controller Operation 320 15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1)Table15-5 describes DACRn fields.Figure 15-3. DRAM Address and Control Register (DACRn) Table15-5. DACRn Field DescriptionsMOTOROLA Chapter15. Synchronous DRAM Controller Module 15-7 321 Table15-5. DACRn Field Descriptions (continued)15-8 MCF5282 Users Manual MOTOROLA SDRAM Controller Operation 322 15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1)The DMRn, Figure 15-4, includes mask bits for the base address and for address attributes. Table15-6 describes DMR n fields.Figure 15-4. DRAM Controller Mask Registers (DMRn) Table15-6. DMRn Field Descriptions 323 15.2.3 General Synchronous Operation Guidelines15.2.3.1 Address Multiplexing15-10 MCF5282 Users Manual MOTOROLA SDRAM Controller Operation 324 Table15-8. MCF5282 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)Table15-9. MCF5282 to SDRAM Interface (8-Bit Port,10-Column Address Lines) Table15-10. MCF5282 to SDRAM Interface (8-Bit Port,11-Column Address Lines) Table15-11. MCF5282 to SDRAM Interface (8-Bit Port,12-Column Address Lines) Table15-12. MCF5282 to SDRAM Interface (8-Bit Port,13-Column Address Lines)MOTOROLA Chapter15. Synchronous DRAM Controller Module 15-11 325 Table15-13. MCF5282 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)Table15-14. MCF5282 to SDRAM Interface (16-Bit Port, 9-Column Address Lines) Table15-15. MCF5282 to SDRAM Interface (16-Bit Port, 10-Column Address Lines) Table15-16. MCF5282 to SDRAM Interface (16-Bit Port, 11-Column Address Lines) Table15-17. MCF5282 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)15-12 MCF5282 Users Manual MOTOROLA SDRAM Controller Operation 326 Table15-18. MCF5282 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)Table15-19. MCF5282 to SDRAM Interface (32-Bit Port, 8-Column Address Lines) Table15-20. MCF5282 to SDRAM Interface (32-Bit Port, 9-Column Address Lines) Table15-21. MCF5282 to SDRAM Interface (32-Bit Port, 10-Column Address Lines) Table15-22. MCF5282 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)MOTOROLA Chapter15. Synchronous DRAM Controller Module 15-13 327 15.2.3.2 SDRAM Byte Strobe ConnectionsFigure 15-5 shows SDRAM connections for port sizes of 32, 16, or 8 bits.Figure 15-5. Connections for External Memory Port Sizes 15.2.3.3 Interfacing Example 15.2.3.4 Burst Page ModeTable15-23. MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines) Table15-24. SDRAM Hardware Connections 329 15.2.3.5 Auto-Refresh Operation330 15.2.3.6 Self-Refresh Operation331 15.2.4 Initialization Sequence333 15.3 SDRAM Example341 Chapter 16 DMA Controller Module357 Chapter 17 Fast Ethernet Controller (FEC)409 Chapter 18 Watchdog Timer Module18.1 Introduction 18.2 Low-Power Mode Operation 410 18.3 Block Diagram18.4 Signals 18.5 Memory Map and Registers 415 Chapter 19 Programmable Interrupt Timer Modules (PIT0PIT3)423 Chapter 20 General Purpose Timer Modules (GPTA and GPTB)20.1 Features20-2 MCF5282 Users Manual MOTOROLA Block Diagram 424 20.2 Block DiagramFigure 20-1. GPT Block Diagram 425 20.3 Low-Power Mode Operation20.4 Signal Description20.4.1 GPTn[2:0] 20.4.2 GPTn3 20.4.3 SYNCn 426 20.5 Memory Map and RegistersMOTOROLA Chapter20. General Purpose Timer Modules (GPTA and GPTB) 20-5 427 20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS)Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS) Table20-3. GPT Modules Memory Map (continued)20-6 MCF5282 Users Manual MOTOROLA Memory Map and Registers 428 20.5.2 GPT Compare Force Register (GPCFORC)Figure 20-4. GPT Output Compare 3 Mask Register (GPTOC3M) 20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M)Table20-4. GPTIOS Field Descriptions Figure 20-3. GPT Input Compare Force Register (GPCFORC) Table20-5. GPTCFORC Field DescriptionsMOTOROLA Chapter20. General Purpose Timer Modules (GPTA and GPTB) 20-7 429 20.5.4 GPT Output Compare 3 Data Register (GPTOC3D)Figure 20-6. GPT Counter Register (GPTCNT) 20.5.5 GPT Counter Register (GPTCNT)Table20-6. GPTOC3M Field Descriptions Figure 20-5. GPT Output Compare 3 Data Register (GPTOC3D) Table20-7. GPTOC3D Field Descriptions20-8 MCF5282 Users Manual MOTOROLA Memory Map and Registers 430 20.5.6 GPT System Control Register 1 (GPTSCR1)Table20-8. GPTCNT Field Descrip tions Figure 20-7. GPT System Control Register 1 (GPTSCR1) Table20-9. GPTSCR1 Field DescriptionsMOTOROLA Chapter20. General Purpose Timer Modules (GPTA and GPTB) 20-9 Figure 20-8. Fast Clear Flag Logic 431 20.5.7 GPT Toggle-On-Overflow Register (GPTTOV)20.5.8 GPT Control Register 1 (GPTCTL1)Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV) Table20-10. GPTTOV Field Description Figure 20-10. GPT Control Register 1 (GPTCTL1)20-10 MCF5282 Users Manual MOTOROLA Memory Map and Registers 432 20.5.9 GPT Control Register 2 (GPTCTL2)20.5.10 GPT Interrupt Enable Register (GPTIE)Figure 20-12. GPT Interrupt Enable Register (GPTIE) Table20-11. GPTCL1 Field Descriptions Figure 20-11. GPT Control Register 2 (GPTCTL2) Table20-12. GPTLCTL 2 Field Descriptions 433 20.5.11 GPT System Control Register 2 (GPTSCR2)MOTOROLA Chapter20. General Purpose Timer Modules (GPTA and GPTB) 20-11 Table20-13. GPTIE Field Descriptions Figure 20-13. GPT System Control Register 2 (GPTSCR2) Table 20-14. GPTSCR2 Field Descriptions20-12 MCF5282 Users Manual MOTOROLA Memory Map and Registers 434 20.5.12 GPT Flag Register 1 (GPTFLG1)20.5.13 GPT Flag Register 2 (GPTFLG2)Figure 20-14. GPT Flag Register 1 (GPTFLG1) Table20-15. GPTFLG1 Field Descriptions Figure 20-15. GPT Flag Register 2 (GPTFLG2) Table20-16. GPTFLG2 Field DescriptionsMOTOROLA Chapter20. General Purpose Timer Modules (GPTA and GPTB) 20-13 435 20.5.14 GPT Channel Registers (GPTCn)20.5.15 Pulse Accumulator Control Register (GPTPACTL)Figure 20-16. GPT Channel[0:3] Register (GPTCn) Table20-17. GPTCn Field Descriptions Figure 20-17. Pulse Accumulator Control Register (GPTPACTL) Table20-18. GPTPACTL Field Descriptions20-14 MCF5282 Users Manual MOTOROLA Memory Map and Registers 436 20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)Figure 20-18. Pulse Accumulator Flag Register (GPTPAFLG) Table20-18. GPTPACTL Field Descriptions (continued)MOTOROLA Chapter20. General Purpose Timer Modules (GPTA and GPTB) 20-15 437 20.5.17 Pulse Accumulator Counter Register (GPTPACNT)Table20-19. GPTPAFLG Field Descriptions Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT) Table20-20. GPTPACR Field Descriptions20-16 MCF5282 Users Manual MOTOROLA Memory Map and Registers 438 20.5.18 GPT Port Data Register (GPTPORT)20.5.19 GPT Port Data Direction Register (GPTDDR)Figure 20-20. GPT Port Data Register (GPTPORT) Table20-21. GPTPORT Field Descriptions Figure 20-21. GPT Port Data Direction Register (GPTDDR) Table 20-22. GPTDDR Field Descriptions 439 20.6 Functional Description443 20.7 ResetTable20-23. GPT Settings and Pin Functions (continued) Table20-24 lists the interrupt requests generated by the timer. 20.8 Interrupts 447 Chapter 21 DMA Timers (DTIM0DTIM3)457 Chapter 22 Queued Serial Peripheral Interface (QSPI) Module475 Chapter 23 UART Modules511 Chapter 24 I2C Interface24.1 Overview 24.2 Interface Features 513 24.3 I2C System Configuration24.4 I2C Protocol 516 24.5 Programming ModelTable24-1 lists the configuration registers used in the I2C interfac e. Table24-2 describes I2ADR fields. 24.5.1 I2C Address Register (I2ADR)Table24-1. I2C Interface Memory Map Figure 24-5. I2C Address Register (I2ADR) Table24-2. I2ADR Field DescriptionsMOTOROLA Chapter24. I2C Interface 24-7 517 24.5.2 I2C Frequency Divider Register (I2FDR)Table24-3 describes I2FDR[IC].Figure 24-6. I2C Frequency Divider Register (I2FDR) Table24-3. I2FDR Field Descriptions24-8 MCF5282 Users Manual MOTOROLA Programming Model 518 24.5.3 I2C Control Register (I2CR)Table24-4 describes I2CR fields.Figure 24-7. I2C Control Register (I2CR) Table24-4. I2CR Field Descriptions MOTOROLA Chapter24. I2C Interface 24-9 519 24.5.4 I2C Status Register (I2SR)This I2SR contains bits that indicate transaction direction and status. Table24-5 describes I2SR fields.Figure 24-8. I2CR Status Register (I2SR) Table24-5. I2SR Field Descriptions 24.5.5 I2C Data I/O Register (I2DR) 520 24.6 I2C Programming Examples527 Chapter 25 FlexCAN585 Chapter 27 Queued Analog-to-Digital Converter (QADC)661 Chapter 28 Reset Controller Module28.1 Features28-2 MCF5282 Users Manual MOTOROLA Block Diagram 662 28.2 Block DiagramFigure 28-1 illustrates the reset controller and is explained in the following sections.Figure 28-1. Reset Controller Block Diagram 28.3 Signals28.3.1 RSTI 28.3.2 RSTOTable28-1. Reset Controller Signal PropertiesName Direction Input Hysteresis Input Synchronization RSTI IY Y MOTOROLA Chapter28. Reset Cont roller Module 28-3 663 28.4 Memory Map and Registers28.4.1 Reset Control Register (RCR)Table28-2. Reset Controller Memory Map Figure 28-2. Reset Control Register (RCR) Table28-3. RCR Field Descriptions28-4 MCF5282 Users Manual MOTOROLA Memory Map and Registers 664 28.4.2 Reset Status Register (RSR)666 28.5 Functional Description28.5.1 Reset Sources28.5.1.1 Power-On Reset 28.5.2.1 Synchronous Reset Requests 28.5.2.2 Internal Reset Request 28.5.2.3 Power-On Reset/Low-Voltage Detect Reset 670 28.5.3 Concurrent Resets673 Chapter 29 Debug Support29.1 Overview 674 29.2 Signal Description675 29.3 Real-Time Trace Support677 29.4 Programming Model29-6 MCF5282 Users Manual MOTOROLA Programming Model Figure 29-4. Debug Programming Model 678 These registers are accessed through the BDM port by the commands, WDMREG andRDMREG, described in Section 29.5.3.3, Command Set Descriptions. These commands contain a 5-bit field, DRc, that specifies the register, as shown in Table29-3. 679 29.4.1 Revision A Shared Debug Resources29-8 MCF5282 Users Manual MOTOROLA Programming Model 680 29.4.2 Address Attribute Trigger Register (AATR)Table29-5 describes AATR fieldsFigure 29-5. Address Attribute Trigger Register (AATR) Table29-5. AATR Field DescriptionsMOTOROLA Chapter29. Debug Support 29-9 681 29.4.3 Address Breakpoint Registers (ABLR, ABHR)Figure 29-6. Address Breakpoint Registers (ABLR, ABHR) Table29-5. AATR Field Descriptions (continued) 682 29.4.4 Configuration/Status Register (CSR)684 29.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)Figure 29-8. Data Breakpoint/Mask Registers (DBR/DBMR) Table29-8. CSR Field Descriptions (continued) 685 29.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)686 29.4.7 Trigger Definition Register (TDR)688 29.5 Background Debug Mode (BDM)709 29.6 Real-Time Debug Support712 29.7 Processor Status, DDATA Definition717 29.8 Motorola-Recommended BDM PinoutThe ColdFire BDM connector, Figure 29-41, is a 26-pin Berg connector arranged 2 x 13.Figure 29-41. Recommended BDM Connector 719 Chapter 30 Chip Configuration Module (CCM)751 Chapter 33 Electrical Characteristics33.1 Maximum Ratings 753 33.2 Thermal CharacteristicsTable33-2 lists thermal resistance values.Table33-2. Th ermal Characteristics The average chip-junction temperature (TJ) in C can be obtained from: 33-4 MCF5282 Users Manual MOTOROLA DC Electrical Specifications 754 33.3 DC Electrical Specifications(2) Solving equations 1 and 2 for K gives:K = PD (TA + 273 C) + QJMA PD 2 (3) Table33-3. DC Electrical Specifications1MOTOROLA Chapter33. Electrical Characteristics 33-5 DC Electrical Specifications 755 Table33-3. DC Elect rical Specifications1 (Continued)33-6 MCF5282 Users Manual MOTOROLA Phase Lock Loop Electrical Specifications 756 33.4 Phase Lock Loop Electrical SpecificationsMOTOROLA Chapter33. Electrical Characteristics 33-7 QADC Electrical Characteristics 757 33.5 QADC Electrical Characteristics759 33.6 Flash Memory CharacteristicsThe Flash memory characteristics are shown in Table33-8 and Table 33-9. Table33-7. QADC Conversi on Specifications (Operating) Table33-8. SGFM Flash Progr am and Erase Characteristics33-10 MCF5282 Users Manual MOTOROLA External Interface Timing Characteristics 760 33.7 External Interface Timing CharacteristicsTable33-10 lists processor bus input timings. Table33-9. SGFM Flash Module Life Characteristics Table33-10. Processor Bus Input Timing SpecificationsMOTOROLA Chapter33. Electrical Characteristics 33-11 Timings listed in Table33-10 are shown in Figure 33-1.Figure 33-1. General Input Timing Requirements 761 33.8 Processor Bus Output Timing Specifications767 33.9 General Purpose I/O TimingTable33-13. GPIO T iming1, 2(VDD = 2.7 to 3.6 V, VSS = 0 V, VDDH = 5 V) 33-18 MCF5282 Users Manual MOTOROLA Reset and Configuration Override Timing 768 33.10 Reset and Configuration Override Timing Figure 33-7. GPIO Timing Table3 3-14. Reset and Configuration Override Timing Table33-13 . GPIO Timing1, 2 (Continued)(VDD = 2.7 to 3.6 V, VSS = 0 V, VDDH = 5 V) MOTOROLA Chapter33. Electrical Characteristics 33-19 I2C Input/Output Timing Specifications Figure 33-8. RSTI and Configuration Override Timing 769 33.11 I2C Input/Output Timing SpecificationsTable33-15 lists specifications for the I2C input timing parameters shown in Figure 33-9.Table33-15. I2C Input Timing Specifications between SCL and SDA Table33-14. Reset an d Configuration Override Timing (Continued)33-20 MCF5282 Users Manual MOTOROLA Fast Ethernet AC Timing Specifications Table33-16 lists specifications for the I2C output timing parameters shown in Figure 33-9. Figure 33-9 shows timing for the values in Table33-15 and Table 33-16.Figure 33-9. I2C Input/Output Timings 770 33.12 Fast Ethernet AC Timing SpecificationsMII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.Table33-16. I2C Output Timing Specifications between SCL and SDA 771 33.12.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)33.12.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)33-22 MCF5282 Users Manual MOTOROLA Fast Ethernet AC Timing Specifications Table33-18 lists MII transmit channel timings. Figure 33-11 shows MII transmit signal timings listed in Table33-18. Figure 33-11. MII Transmit Signal Timing Diagram 772 33.12.3 MII Async Inputs Signal Timing (ECRS and ECOL)Figure 33-12. MII Async Inputs Timing Diagram Table33-18. MII Transmit Signal Timing Table33-19. MII Async In puts Signal TimingETXEN MOTOROLA Chapter33. Electrical Characteristics 33-23 773 33.12.4 MII Serial Management Channel Timing (EMDIO and EMDC)Figure 33-13 shows MII serial management channel timings listed in Table33-20. Figure 33-13. MII Serial Management Channel Timing Diagram Table33-20. MII Serial Management Channel Timing33-24 MCF5282 Users Manual MOTOROLA DMA Timer Module AC Timing Specifications 774 33.13 DMA Timer Module AC Timing SpecificationsTable33-21 lists timer module AC timings. 33.14 QSPI Electrical Specifications Table33-22 lists QSPI timings. The values in Table33-22 correspond to Figure 33-14.Figure 33-14. QSPI Timing Table33-21. Timer Module AC Timing Specifications Table33-22. QSPI Modules AC Timing SpecificationsMOTOROLA Chapter33. Electrical Characteristics 33-25 JTAG and Boundary Scan Timing 775 33.15 JTAG and Boundary Scan TimingFigure 33-15. Test Clock Input Timing Table33-23. JTAG and Boun dary Scan TimingNum Characteristics Symbol Min Max Unit 33-26 MCF5282 Users Manual MOTOROLA JTAG and Boundary Scan Timing 776 Figure 33-16. Boundary Scan (JTAG) TimingFigure 33-17. Test Access Port Timing Figure 33-18. TRST TimingMOTOROLA Chapter33. Electrical Characteristics 33-27 Debug AC Timing Specifications Figure 33-19. BKPT Timing 777 33.16 Debug AC Timing SpecificationsTable33-24 lists specifications for the debug AC timing parameters shown in Figure 33-21.Table 33-24. Debug AC Timing SpecificationB2b 33-28 MCF5282 Users Manual MOTOROLA Debug AC Timing Specifications 778 Figure 33-20 shows real-time trace timing for the values in Table33-24.Figure 33-20. Real-Time Trace AC Timing Figure 33-21 shows BDM serial port AC timing for the values in Table 33-24.Figure 33-21. BDM Serial Port AC TimingMOTOROLA AppendixA. Register Memory Map A-1 779 Appendix A Register Memory Map
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