SDRAM Controller Operation

15.2.2.2DRAM Address and Control Registers (DACR0/DACR1)

The DACRn registers, shown in Figure 15-3,contain the base address compare value and the control bits for memory blocks 0 and 1 of the SDRAM controller. Address and timing are also controlled by bits in DACRn.

Field

Reset

R/W Address

31

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

BA

 

RE

CASL

CBM

 

IMRS

PS

IP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Uninitialized

 

 

 

0

 

 

Uninitialized

 

 

 

0

 

Uninitialized

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

IPSBAR+0x048 (DACR0); 0x050 (DACR1)

Figure 15-3. DRAM Address and Control Register (DACRn)

Table 15-5describes DACRn fields.

 

 

 

 

 

 

 

 

 

Table 15-5. DACRn Field Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

Name

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

31–18

BA

 

Base address register. With DCMR[BAM], determines the address range in which the associated DRAM block is

 

 

 

located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits

 

 

 

match, the address hits in the associated DRAM block. BA functions the same as in asynchronous operation.

 

 

 

 

 

 

 

 

17–16

Reserved, should be cleared.

 

 

 

 

 

 

 

 

 

 

15

RE

 

Refresh enable. Determines when the DRAM controller generates a refresh cycle to the DRAM block.

 

 

 

0 Do not refresh associated DRAM block

 

 

 

 

 

 

 

 

1 Refresh associated DRAM block

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

Reserved, should be cleared.

 

 

 

 

 

 

 

 

 

 

 

 

13–12

CASL

 

 

 

latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with

 

CAS

 

 

 

manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Number of Bus Clocks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CASL= 00

CASL = 01

CASL= 10

CASL= 11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRCD—SRAS

assertion to SCAS assertion

1

2

3

3

 

 

 

 

 

 

 

 

 

 

assertion to data out

1

2

3

3

 

 

 

 

 

tCASL—SCAS

 

 

 

 

tRASACTVcommand to precharge command

2

4

6

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRP—Precharge command to ACTV command

1

2

3

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRWL,tRDL—Last data input to precharge command

1

1

1

1

 

 

 

 

 

tEP—Last data out to precharge command

1

1

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

Reserved, should be cleared.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15-6

MCF5282 User’s Manual

MOTOROLA

Page 320
Image 320
Motorola MCF5282 Dram Address and Control Registers DACR0/DACR1, 5describes DACRn fields, DACRn Field Descriptions, Bit