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Motorola MCF5282, MCF5281 user manual Gated Mode, Single Scan Timing

Models: MCF5282 MCF5281

1 816

Page 650

Signal Connection Considerations

When the gate closes, the active conversion completes before the queue goes idle. When Q1 completes, both the CF1 bit sets and the SSE bit clears.

In this mode, the PF1 bit sets to reflect that a gate closing occurred before the queue completed.

Figure 27-48shows the timing for conversions in externally gated continuous scan mode with the same assumptions as in Figure 27-47.

At the end of Q1,the completion flag CF1 sets and the queue restarts. If the queue starts a second time and completes, the trigger overrun flag TOR1 sets.

TRIG1 (GATE)

EOC

CWP

LAST

CCW0

CWPQ1

LAST

Q1 RES	LAST
SSE

CF1

PF1

CCW0

CCW1

CCW0

CCW1

CCW2

CCW0

CCW1

CCW3

CCW2 CCW3

R2		R3

Figure 27-47. Gated Mode, Single Scan Timing

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MCF5282 User’s Manual

MOTOROLA

Page 650

Image 650

Motorola MCF5282, MCF5281 user manual Gated Mode, Single Scan Timing

Contents

MCF5282 ColdFire Microcontroller User’s Manual HOW to Reach US USA/EUROPE/LOCATIONS not Listed IND IND Contents Chapter Enhanced Multiply-Accumulate Unit Emac Timing Assumptions Move Instruction Execution TimesColdFire Flash Module CFM Chapter CacheChapter Static RAM Sram Chapter Power Management Chapter System Control Module SCMClock Module Interrupt Controller ModulesChapter Chip Select Module Signal DescriptionsChapter Edge Port Module Eport Chapter External Interface Module EIMChapter Synchronous Dram Controller Module Chapter DMA Controller ModuleChapter Fast Ethernet Controller FEC Chapter General Purpose Timer Modules Gpta and Gptb Chapter Watchdog Timer ModuleChapter Programmable Interrupt Timer Modules PIT0-PIT3 20.3 Chapter DMA Timers DTIM0-DTIM3 Chapter Queued Serial Peripheral Interface Qspi ModuleChapter Uart Modules Chapter I2C InterfaceChapter FlexCAN Chapter General Purpose I/O Module Chapter Queued Analog-to-Digital Converter Qadc27.4.7 Reset Controller Module Chapter Debug SupportChapter Chip Configuration Module CCM Chapter Ieee 1149.1 Test Access Port JtagAppendix a Register Memory Map Electrical CharacteristicsChapter Mechanical Data Paragraph Title Number 31.6.2 Nonscan Chain Operation 31-12Illustrations Title Number10-7 13-4 17-13 20-20 23-10 25-31 Qadc Status Register 0 QASR0 27-22 27-12 27-53 29-39WDMREG BDM Command Format 29-36 29-40 Tables Charge Pump Current and MFD in Normal Mode Operation 10-13 15-18 17-30 20-23 25-21 27-13 29-43 33-21 Timer Module AC Timing Specifications 33-24 33-22 Audience OrganizationOrganization Xlv ColdFire Documentation Suggested ReadingGeneral Information Conventions Meaning Acronyms and AbbreviationsTable i. Acronyms and Abbreviated Terms Operand Syntax Terminology ConventionsTable ii. Notational Conventions Opcode WildcardPort Name ACCCCR PSTLSW MSWTable iii. Revision History Revision HistoryTable iii provides a revision history for this document SSTFrsr Revision Date Substantive ChangesNumber Release Liv 10.3.6/10-11 RAMBAR.’Revision Number Substantive Changes Section/PageMCF5282 Key Features Chapter OverviewMCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Block Diagram Version 2 ColdFire Core Cache ConfigurationConfiguration Tag Address Data Array Address CacheDebug Module SramFlash System Control Module External Interface Module EIMGeneral Input/Output Ports Power ManagementChip Select Interrupt Controllers INTC0/INTC1Test Access Port Uart ModulesPeriodic Interrupt Timers PIT0-PIT3 DMA Timers DTIM0-DTIM3General-Purpose Timers GPTA/GPTB Reset Software Watchdog TimerPhase Locked Loop PLL DMA ControllerMCF5282-Specific Features MCF5282-Specific Features Fifo Processor PipelinesIAG DsocProcessor Register Description User Programming ModelStack Pointer A7 Data Registers D0-D7Address Registers A0-A6 Program Counter PCCondition Code Register CCR Bits Name DescriptionEmac Programming Model Supervisor Programming ModelBits Status Register SRSystem Byte Condition Code Register CCR Supervisor/User Stack Pointers A7 and OTHERA7 Vector Base Register VBR Access Control Registers ACR0, ACR1Programming Model Cache Control Register CacrLocal Memory Registers Additions to the Instruction Set ArchitectureName CPU Space Rc Written with Register Name Instruction Description Exception Processing OverviewISA Revision A+ New Instructions Exception Vector Assignments Vector Stacked Program Assignment NumberS Offset Hex Counter0x100-0x3FC Next Exception Stack Frame DefinitionFormat Field Encodings Processor Exceptions Access Error ExceptionFault Status Encodings FS30 DefinitionDivide-By-Zero Address Error ExceptionIllegal Instruction Exception Privilege ViolationDebug Interrupt Unimplemented Line-A OpcodeUnimplemented Line-F Opcode Reset Exception RTE and Format Error ExceptionFault-on-Fault Halt Trap Instruction ExceptionVER REV MAC DIV Emac FPU MMU ISA DebugMAC D0 Hardware Configuration Info Field DescriptionVER ICA ICA Icsiz RAM0SIZ ROM0SIZBusw DCA Dcsiz RAM1SIZ ROM1SIZ 16KB RAM 4KB RAM8KB RAM 32KB RAMInstruction Execution Timing Timing AssumptionsAddress10 Size Kbus Additional Operations CR/W Move Instruction Execution Times10. Misaligned Operand References Source Destination Ax+ D16,Ax D8,Ax,Xi Xxx.wl 11. Move Byte and Word Execution Times12. Move Long Execution Times 13. One Operand Instruction Execution Times Standard One Operand Instruction Execution TimesStandard Two Operand Instruction Execution Times 14. Two Operand Instruction Execution TimesStandard Two Operand Instruction Execution Times Effective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl Miscellaneous Instruction Execution Times15. Miscellaneous Instruction Execution Times D16,PC D8,PC,Xn*SFEffective Address Opcode An+ D16,An D8,An,X Xxx.wl #xxx Emac Instruction Execution Times16. Emac Instruction Execution Times 17. General Branch Instruction Execution Times Branch Instruction Execution TimesColdFire Instruction Set Architecture Enhancements 18. BRA, Bcc Instruction Execution TimesAttributes OperationAssembler Syntax Instruction FormatCondition Codes Byte Reverse Register ByterevAssembler Syntax BYTEREV.L Dx Attributes Find First One in Register Old Dx310 New Dx310Assembler SyntaxSTRLDSR #data Store/Load Status Register StrldsrSupported Starting with ISA A+ Chapter Enhanced Multiply-Accumulate Unit Emac Multiply-Accumulate UnitMultiply-Accumulate Functionality Diagram Introduction to the MACGeneral Operation Infinite Impulse Response IIR FilterFractional Alignment Motorola 1describes Macsr fields Memory Map/Register SetMAC Status Register Macsr Macsr Field Descriptions Summary of S/U, F/I, and R/T Control Bits Fractional Operation ModeRounding Operational ModesSaving and Restoring the Emac Programming Model MULS/MULU Following code performs the Emac state restoreMask Register Mask MAC.sz Ry,RxSF,eay&,Rw Emac Instruction Execution Times Command Mnemonic DescriptionEmac Instruction Set Summary 3summarizes Emac unit instructionsAccumulator Mac Old Mov New Data RepresentationMac Mov MAC Opcodes Two’s Complement, Signed Fractional EquationMACSR.V = Emac Instruction Set Summary MACSR.Z = Emac Instruction Set Summary Motorola Emac Instruction Set Summary MCF5282 User’s Manual This chapter describes the MCF5282 cache operation Cache FeaturesCache Physical Organization Cache Physical Organization Cache Operation Interaction with Other ModulesMemory Reference Attributes Cache Coherency and InvalidationCLNF10 Longword Address Bits Cache Miss Fetch Algorithm/Line FillsInitial Fetch Offset vs. Clnf Bits Instruction Cache Operation as Defined by CACR31 CACR31 CACR10 Type of Instruction Fetch DescriptionCache Registers Cache Programming ModelCache Registers Memory Map Cache Control Register CacrCeib DCM Dbwe DWP Eusp Clnf Cenb CPDCinv Didi Disd Invi Invd CenbCeib CACR23 CACR22 CACR21 CACR20 Configuration Operation Cache Configuration as Defined by CACR31, 23CACR31 CACR23 CACR22 Configuration Description Cache Invalidate All as Defined by CACR23, 22, 21Bufw Access Control Registers ACR0, ACR1External Fetch Size Based on Miss Address and Clnf BWE Between the processors local bus and the external busSram Programming Model Sram FeaturesSram Operation PRI1, PRI2 Sram Base Address Register RambarPRI1 PRI2 SPV PRI12 Upper Bank Lower Bank PrioritySram Initialization Sram Base Address RegisterSram Initialization Code Power ManagementTypical Rambar Setting Examples Following loop initializes the entire Sram to zeroSram Programming Model Sram Programming Model MCF5282 User’s Manual Features Chapter ColdFire Flash Module CFMBlock Diagram CFM Block Diagram Memory Map CFM Array Memory MapFlash Base Address Register Flashbar CFM Configuration FieldCFM Configuration Field Address Offset from array base Size DescriptionMemory Map BA30 BA29 Register Descriptions CFM Configuration Register CfmcrCFM Registers Flash registers are described in this subsectionBits Name Description CFM Clock Divider Register CfmclkdCfmcr Field Descriptions Divld PRDIV8CFM Security Register Cfmsec Cfmclkd Field DescriptionsCfmsec Field Descriptions SEC150 DescriptionProt CFM Protection Register CfmprotCfmprot Field Descriptions PROTECT2 CFM Supervisor Access Register CfmsaccPROTECT31 SectorData CFM Data Access Register CfmdaccCfmsacc Field Descriptions 10. Cfmustat Field Descriptions CFM User Status Register CfmustatOnly one Cfmustat bit should be cleared at a time Cbeif Ccif Pviol Accerr BlankCommand Name Description CFM Command Register Cfmcmd12. Cfmcmd User Mode Commands Write Operations CFM OperationRead Operations Program and Erase OperationsConsider the following example for fSYS = 66 MHz Setting the Cfmclkd RegisterThus the Flash state machine clock will be Program, Erase, and Verify Sequences 13. Flash User Commands Flash Valid Commands13summarizes the valid Flash user commands Meaning Description13. Example Program Algorithm Stop Mode Flash User Mode Illegal OperationsMaster Mode Flash Security OperationErase Verify Check ResetBack Door Access 14. CFM Interrupt Sources Interrupt Source Interrupt Flag Local EnableInterrupts Cbeif CbeieInterrupts MCF5282 User’s Manual Memory Map and Registers Programming ModelMemory Map Low-Power Interrupt Control Register LpicrChip Configuration Module Memory Map Following subsection describes the PMM registersLpicr Field Description EnbstopXlpmipl Interrupts Level Needed to Exit Low-Power Mode Low-Power Control Register LpcrXlpmipl Settings Lpmd Stpmd LvdsePLL/CLKOUT Stop Mode Operation Low-Power ModesLow-Power Modes Functional DescriptionDoze Mode Run ModeWait Mode Stop ModePeripheral Shut Down Peripheral Behavior in Low-Power ModesStatic Random-Access Memory Sram ColdFire CoreDMA Controller DMAC0-DMA3 Sdram Controller SdramcChip Select Module Uart Modules UART0, UART1, and UART2Queued Serial Peripheral Interface Qspi DMA Timers DMAT0-DMAT32.9 I2C Module Fast Ethernet Controller FEC Reset ControllerInterrupt Controllers INTC0, INTC1 2.14 I/O PortsChip Configuration Module Clock ModuleEdge Port Watchdog TimerProgrammable Interrupt Timers PIT0, PIT1, PIT2 and PIT3 Queued Analog-to-Digital Converter QadcGeneral Purpose Timers Gpta and Gptb FlexCANFunctional Description ColdFire Flash Module 2.25 BDM Summary of Peripheral State During Low-Power ModesCPU and Peripherals in Low-Power Modes JtagJtag QadcBDM Functional Description MCF5282 User’s Manual Features Overview3124 2316 158 Memory Map and Register DefinitionSCM Register Map Cache Register DescriptionsInternal Peripheral System Base Address Register Ipsbar Memory Base Address Register Rambar Ipsbar Field DescriptionMemory Base Address Register Rambar Rambar Field Description BDECrsr Field Descriptions Core Reset Status Register CrsrCore Watchdog Control Register Cwcr Register Descriptions Core Watchdog Timer Delay CWT CWT Time-Out PeriodCore Watchdog Service Register Cwsr Internal Bus ArbitrationFEC Sdramc SRAM1 Mpark Rambar CPU DMA EIMMarb Arbitration Algorithms Round-Robin ModeOverview Bus Master Park Register Mpark Fixed ModeFixed Timeout Prklast Lckouttime M2PEN BCR24BIT M3PRTY M2PRTY M0PRTY M1PRTYMpark Field Description System Access Control Unit Sacu Features3128 2724 2320 1916 1512 118 Memory Map/Register DefinitionSacu Register Memory Map PACR1 PACR2 PACR3PACR6 Peripheral Access Control Registers Pacr 0-PACR8Master Privilege Register MPR Ipsbar Offset Name Modules Controlled 12. Peripheral Access Control Registers PACRsBits Supervisor Mode User Mode DTIM0 DTIM1 UART2Qspi DTIM2 DTIM3Gpacr Field Descriptions 13. Grouped PeripheralAccess Control Register14. Gpacr Accessctrl Bit Encodings GPACR0 15. Gpacr Address SpaceRegister Space Protected Modules Protected Ipsbar Offset EPORT, WDOG, PIT0-PIT3, QADC, GPTA, GptbNormal PLL Mode Modes of OperationExternal Clock Mode Low-power Mode Operation2 11 PLL Mode Clock Module Operation in Low-power ModesBlock Diagram Clock Module Block DiagramExtal Signal DescriptionsSignal Properties Name FunctionMemory Map and Registers Lolre MFD2 MFD1 MFD0 Locre Register DescriptionsSynthesizer Control Register Syncr Locen Disclk Fwkup STPMD1 STPMD0RFD MFDMFD20 OSC Synthesizer Status Register SynsrStpmd PllmodeSynsr Field Descriptions LocksSystem Clock Modes Clock ModeFunctional Description System Clock ModesSystem Clock Generation Clock Operation During ResetSystem Clock Mode PLL Options Clock Out and Clock In RelationshipsPhase and Frequency Detector PFD PLL OperationVoltage Control Output VCO Charge Pump Current and MFD in Normal Mode OperationCharge Pump/Loop Filter Multiplication Factor Divider MFDPLL Lock Detection PLL Loss of Lock Reset PLL Loss of Lock ConditionsAlternate Clock Selection Loss of Clock ResetLoss of Clock Detection Loss of Clock SummaryLoss of Clock in Stop Mode 10. Stop Mode Operation Sheet 1Stop 10. Stop Mode Operation Sheet 2Expected PLL Action ‘LC NRM ‘LK 10. Stop Mode Operation Sheet 3NRM ‘LC ‘LK 10. Stop Mode Operation Sheet 4 PLLClock 10. Stop Mode Operation Sheet 5Lose reference ModesFunctional Description MCF5282 User’s Manual Chapter Interrupt Controller Modules 10.1 68K/ColdFire Interrupt Architecture Overview68K/ColdFire Interrupt Architecture Overview Interrupt Prioritization Interrupt Controller Theory of OperationInterrupt Recognition Interrupt Priority Within a LevelInterrupt Vector Determination Interrupt Controller Memory Map Memory MapInterrupt Controller Base Addresses Interrupt Controller Number Base AddressInterrupt Pending Registers IPRHn, IPRLn INT Maskall Interrupt Mask Register IMRHn, IMRLnIntmask Intfrc Interrupt Force Registers INTFRCHn, INTFRCLnIMRLn Field Descriptions Interrupt Request Level Register IRLRn IRQ11. IACKLPRn Field Descriptions Interrupt Acknowledge Level and Priority Register IACKLPRnInterrupt Control Register ICRnx, x = 1, 2 Level PRI13. Interrupt Source Assignment for INTC0 Interrupt Sources12. ICRnx Field Descriptions DTIM1 CAP/REF IIFDTIM0 CAP/REF DTIM2 CAP/REFPIT1 PIF Gptb TOFPIT0 PIF PIT2 PIFSoftware and Level n Iack Registers SWIACKR, L1IACK-L7IACK 14. Interrupt Source Assignment for INTC1Prioritization Between Interrupt Controllers VectorLow-Power Wakeup Operation 10-18 Ipbus Low-Power Mode OperationIntroduction Interrupt/General-Purpose I/O Pin Descriptions Edge Port Module Operation in Low-power ModesLow-power Mode Eport Operation Mode Exit Edge Port Module Memory Map Bits AccessRegisters EPPA7 Eport Pin Assignment Register EpparEport Data Direction Register Epddr EPPA5 EPPA4 EPPA3 EPPA2 EPPA1Epdd Field Descriptions Edge Port Interrupt Enable Register EpierEdge Port Data Register Epdr Epdr Field Descriptions Edge Port Pin Data Register EppdrEdge Port Flag Register Epfr Epfr Field Descriptions EPF7-EPF111-8 Chip Select Module Signals Chip Select Module Signals1lists signals used by the chip select module Signal DescriptionD3124 D2316 D158 D70 Byte Enables/Byte Write Enable Signal SettingsTransfer Size Port Size Chip Select Operation General Chip Select Operation12.3.1.1 8-, 16-, and 32-Bit Port Sizing External Boot Chip Select OperationAccesses by Matches in CSARs and DACRs BS2 BS1 BS0Chip Select Registers D1918 External Boot Chip Select ConfigurationD1918 Boot Device/Data Port Size Chip Select RegistersCSARs, -2,specify the chip select base addresses Chip Select Module RegistersChip Select Address Registers CSAR0-CSAR6 6describes CsarbaCSARn Field Description Chip Select Mask Registers CSMR0-CSMR67describes Csmr fields Csmr n Field DescriptionsSD,UC Chip Select Control Registers CSCR0-CSCR68describes CSCRn fields PS1 PS0 BEM Bstr BstwCSCRn Field Descriptions No internal TA is asserted. Cycle is terminated externally12-10 Signal Name Description Clkout Edge Bus and Control SignalsColdFire Bus Signal Summary TIP Bus CharacteristicsData Transfer Operation Chip-Select Module Output Timing Diagram Bus Cycle ExecutionAccesses by Matches in CSCRs and DACRs State Cycle Data Transfer Cycle StatesBus Cycle States Read Cycle MCF5282 System3describes the six states of a basic write cycle Write cycle timing diagram is shown in FigureWrite Cycle Fast Termination Cycles Read Cycle with Fast TerminationBack-to-Back Bus Cycles Burst CyclesLine Transfers Allowable Line Access PatternsA32 Longword Accesses Line Read Bus Cycles13shows timing when internal termination is used Line Write Bus Cycles 16. Line Write Burst 2-1-1-1, Internal/External TerminationMisaligned Operands 17shows a line burst write with one wait-state insertion19. Example of a Misaligned Longword Transfer 32-Bit Port 13-16 Chapter Signal Descriptions MCF5282 Block Diagram with Signal Interfaces Sdram Controller Signals MCF5282 Signal DescriptionSignal Name Abbreviation Function External Memory Interface Chip Configuration Module Signal Name Abbreviation FunctionClock and Reset Signals External Interrupt Signals2C Signals Queued Serial Peripheral Interface Qspi SignalsFlexCAN Signals Uart SignalsAnalog-to-Digital Converter Qadc Signals General Purpose Timer SignalsDMA Timer Signals Debug Support SignalsPower and Reference Signals 2lists signals in alphabetical order by abbreviated nameTest Signals MCF5282 Alphabetical Signal Index Abbreviation FunctionVddpll TCK Secondary MCF5282 Signals and Pin Numbers Sorted by FunctionChip Configuration/Mode Selection External Memory Interface and PortsExternal Interrupts Port Chip SelectsSdram Controller EthernetFlexCAN General Purpose Timers UARTsDebug and Jtag Test Port Control DMA TimersQueued Analog-to-Digital Converter Qadc Test Single-Chip ModePower Supplies Pin Reset States at Reset Single-Chip Mode External Boot ModeListing of signals that do not default to a Gpio function Signal Reset Clock and Reset SignalsAddress Bus A230 14.2 MCF5282 External SignalsExternal Interface Module EIM Signals Data Bus D310Transfer Acknowledge TA Output Enable OETransfer Error Acknowledge TEA Read/Write R/WChip Selects CS60 Transfer Start TSTransfer In Progress TIP Transfer Size EncodingSdram Controller Signals Clock and Reset Signals Chip Configuration SignalsExternal Interrupt Signals Ethernet Module SignalsReceive Clock Erxclk Transmit Error EtxerCollision Ecol Receive Data Valid ErxdvQueued Serial Peripheral Interface Qspi Signals Uart Module Signals FlexCAN Signals14.2.9 I2C Signals General Purpose Timer Signals DMA Timer Signals Analog-to-Digital Converter Signals Debug Support Signals Development Serial Output/Test Data DSO/TDO Breakpoint/Test Mode Select BKPT/TMSDevelopment Serial Input/Test Data DSI/TDI Test Clock TclkProcessor Status Outputs PST30 Test SignalsDebug Data DDATA30 Test TestPower and Reference Signals 14-34 Overview DefinitionsDACR1 Block Diagram and Major ComponentsDACR0 Scas Sras Scke SDRAMCS10 DramwSdram Controller Operation Sdram CommandsCommand Definition Memory Map for Sdramc Registers Dram Controller Signals2describes the behavior of Dram signals in synchronous mode Dram controller registers memory map is shown in Table4describes DCR fields Dram Control Register DCRDCR, shown in -2,controls refresh logic DCR Field DescriptionsDACRn Field Descriptions Dram Address and Control Registers DACR0/DACR15describes DACRn fields Bit15-7 6describes DMRn fields Bit Associated Access Type Access DefinitionDram Controller Mask Registers DMR0/DMR1 DMRn Field DescriptionsGeneric Address Multiplexing Scheme General Synchronous Operation GuidelinesAddress Multiplexing Address Pin Row Address Column AddressMCF5282 Pins Row ColumnPins Row Column 15-12 Sdram Byte Strobe Connections Burst Page ModePins MCF5282 Interfacing ExampleBurst Read Sdram Access Burst Write Sdram Access Auto-Refresh OperationSelf-Refresh Operation Auto-Refresh OperationInitialization Sequence Self-Refresh OperationMode Register Settings Sdram Example 25. Sdram Example SpecificationsParameter Specification ClkoutDacr Initialization Sdram Interface ConfigurationDCR Initialization 26. Sdram Hardware Connections28. Dacr Initialization Values Bits Name Setting DescriptionDACRs should be programmed as shown in Figure Casl CBM ImrsDMR Initialization 29. DMR0 Initialization Values31. Mode Register Mapping to MCF5282 A310 Mode Register Initialization30. Mode Register Initialization MCF5282 Pins Sdram Pins Mode Register InitializationPrecharge Sequence Mode Register Initialization SequenceInitialization Code Refresh Sequence15-25 15-26 Chapter DMA Controller Module DMA Module Features Channel 0 Channel 1 Channel 2 ChannelDMA Request Control Dmareqc DMA Transfer Overview DMADMA Controller Module Programming Model Memory Map for DMA Controller Module RegistersSAR Source Address Registers SAR0-SAR3Destination Address Registers DAR0-DAR3 DARByte Count Registers BCR0-BCR3 BCRDCRn Field Descriptions DMA Control Registers DCR0-DCR33describes DCRn fields BWC Sinc Ssize Dinc Dsize StartBWC Encoding BCR24BIT =DSR n Field Descriptions DMA Status Registers DSR0-DSR34describes DSRn fields BSY DMA Controller Module Functional DescriptionTransfer Requests Cycle-Steal and Continuous Modes DoneData Transfer Modes Dual-Address TransfersProgramming the DMA Controller Module Channel Initialization and StartupChannel Prioritization Data Transfer Auto-AlignmentTermination Bandwidth Control16-16 Chapter Fast Ethernet Controller FEC 17.2.2.1 10 Mbps and 100 Mbps MII Interface Full and Half Duplex OperationInterface Options Primary operational modes are described in this sectionInternal Loopback 17.2.2.2 10 Mpbs 7-Wire Interface OperationAddress Recognition Options FEC Top-Level Functional Diagram PAD17-5 Hardware Controlled Initialization Initialization SequenceUser Initialization Prior to Asserting Ecretheren Ecretheren De-Assertion Effect on FECFEC User Initialization Before Ecretheren Microcontroller InitializationUser Initialization After Asserting Ecretheren Microcontroller InitializationSignal Description Emac pin MII ModeWire Mode Configuration Network Interface OptionsFEC Frame Transmission FEC Frame Reception Ethernet Address Recognition Ethernet Address Recognition-Receive Block Decisions Hash Algorithm Ethernet Address Recognitionq-Microcode DecisionsDestination Address to 6-Bit Hash Bit DA Bit Hash Hash Decimal Hex Value17-15 Pause Frame Field Specification Full Duplex Flow ControlInternal and External Loopback Inter-Packet Gap IPG TimeCollision Handling Ethernet Error-Handling Procedure Transmission ErrorsReception Errors HeartbeatModule Memory Map Top Level Module Memory MapDetailed Memory Map Control/Status Registers 10. FEC Register Memory MapMIB Block Counters Memory Map 11. MIB Counters Memory Map Mnemonic Description OffsetFollowing sections describe each register in detail RegistersEthernet Interrupt Event Register EIR Hberr Ieeetsqe Babr Babt GRA TXF TXB RXF RXB MII Eberr17-25 Babr Babt GRA TXF TXB RXF RXB MII Interrupt Mask Register EimrReceive Descriptor Active Register Rdar Transmit Descriptor Active Register Tdar RdesactiveXdesactive Etheren ResetEthernet Control Register ECR Data MII Management Frame Register Mmfr16. ECR Field Descriptions 17. Mmfr Field Descriptions Bit Name DescriptionDispreamble MII Speed Control Register MscrDispreamble Miispeed MIB Control Register Mibc Mibdisable MibidleMibdisable 19. Programming Examples for MscrFCE Bcrej Prom Miimode DRT Loop Receive Control Register RCRMaxfl FCEGTS Transmit Control Register TCRTfcpause Fden Tfcpause Physical Address Low Register Palr22. TCR Field Descriptions PADDR2 Physical Address High Register PaurPADDR1 Type24. Paur Field Descriptions Opcode/Pause Duration Register OPDDescriptor Individual Upper Address Register Iaur OpcodeBits Name Descriptions Descriptor Individual Lower Address IalrIADDR1 IADDR227. Ialr Field Descriptions Descriptor Group Upper Address GaurDescriptor Group Lower Address Galr GADDR1Xwmrk Fifo Transmit Fifo Watermark Register TfwrGADDR2 Rbound Fifo Receive Bound Register Frbr30. Tfwr Field Descriptions Rfstart Fifo Receive Start Register FrsrReceive Descriptor Ring Start Erdsr Xdesstart Transmit Buffer Descriptor Ring Start EtsdrRdesstart Rbufsize Receive Buffer Size Register Emrbr34. Etdsr Field Descriptions Driver/DMA Operation with Transmit BDs Buffer DescriptorsDriver/DMA Operation with Buffer Descriptors Driver/DMA Operation with Receive BDs Ethernet Receive Buffer Descriptor RxBD RO1 RO2RO1 36. Receive Buffer Descriptor Field DefinitionsWord Location Field Name Description ErdsrEthernet Transmit Buffer Descriptor TxBD TO1 TO2 ABC TO117-51 17-52 Watchdog Module Operation in Low-power Modes Low-power Mode Watchdog Operation Mode ExitRefer to -2for an overview of the watchdog memory map SignalsWatchdog timer module has no off-chip signals Watchdog Control Register WCR 16-bit WCR configures watchdog timer operationWatchdog Timer Module Memory Map Watchdog Modulus Register WMR WCR Field DescriptionsWMR Field Descriptions Watchdog Service Register WSRWatchdog Count Register Wcntr WC9 WC8WS9 WS8 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0Chapter Programmable Interrupt Timer Modules PIT0-PIT3 Low-power Mode PIT Operation Mode Exit PIT module has no off-chip signalsPIT Module Operation in Low-power Modes Programmable Interrupt Timer Modules Memory Map Ipsbar Offset Access For PITx Bits AddressDoze Halted OVW PIE PIF RLD PIT Control and Status Register PcsrPRE3 PRE2 PRE1 PRE0 PREPIT Modulus Register PMR PIFThis subsection describes the PIT functional operation Set-and-Forget Timer OperationPIT Count Register Pcntr System clock Free-Running Timer OperationTimeout Specifications PIT Clock Counter4shows the interrupt request generated by the PIT Interrupt Request Flag Enable Bit TimeoutInterrupt Operation PIT Interrupt RequestsChapter General Purpose Timer Modules Gpta and Gptb GPT Block Diagram GPTn20 Signal DescriptionFunction Reset State Pull-up Name Register Bit PinSYNCn Ipsbar Offset Bits AccessGPTn3 GPT Modules Memory MapGPT Input Capture/Output Compare Select Register Gptios IOSGptios Field Descriptions GPT Compare Force Register GpcforcGPT Output Compare 3 Mask Register GPTOC3M FOCGPTOC3M Field Descriptions GPT Output Compare 3 Data Register GPTOC3DGPT Counter Register Gptcnt OC3DGpten Tffca GPT System Control Register 1 GPTSCR1Gptcnt Field Descriptions GptenTOV GPT Toggle-On-Overflow Register GpttovGPT Control Register 1 GPTCTL1 OM3 OL3 OM211. GPTCL1 Field Descriptions GPT Interrupt Enable Register GptieGPT Control Register 2 GPTCTL2 EDG3B EDG3A EDG2B EDG2AGPT System Control Register 2 GPTSCR2 13. Gptie Field DescriptionsGPT Flag Register 1 GPTFLG1 GPT Flag Register 2 GPTFLG2Ccnt GPT Channel Registers GPTCnPulse Accumulator Control Register Gptpactl PAE Pamod Pedge CLK Paovi PAIPaovf Paif Pulse Accumulator Flag Register GptpaflgPaclk Pacnt Pulse Accumulator Counter Register Gptpacnt19. Gptpaflg Field Descriptions 22. Gptddr Field Descriptions GPT Port Data Register GptportGPT Port Data Direction Register Gptddr PorttOutput Compare PrescalerInput Capture Event Counter Mode Pulse AccumulatorPulse Accumulator Gated Time Accumulation ModeGeneral-Purpose I/O Ports OM3 OL3Dir Function 23. GPT Settings and Pin FunctionsEDGx OMx OC3Mx Pin Data Driven Comments Interrupt Request Flag Enable Bit Reset24lists the interrupt requests generated by the timer InterruptsPulse Accumulator Overflow Paovf Timer Overflow TOFGPT Channel Interrupts CnF Pulse Accumulator Input Paif20-23 20-24 Chapter DMA Timers DTIM0-DTIM3 Prescaler DMA Timer Programming ModelKey Features DMA Timer Module Memory Map Capture ModeOutput Mode Reference CompareDMA Timer Mode Registers DTMRn Orri FRR CLK RSTDTMRn Field Descriptions DMA Timer Extended Mode Registers DTXMRn2describes the DTMRn fields DTXMR3DTXMRn Field Descriptions DMA Timer Event Registers DTERn3describes the DTXMRn fields 4describes the DTERn fields DMA Timer Reference Registers DTRRnDMA Timer Capture Registers DTCRn DTERn Field DescriptionsUsing the DMA Timer Modules DMA Timer Counters DTCNnCode Example Calculating Time-Out Values T0LOOPChapter Queued Serial Peripheral Interface Qspi Module Module DescriptionQspiclk Interface and SignalsQspi RAM Operation Qspi Input and Output Signals and FunctionsSignal Name Hi-Z or Actively Driven Function Internal Bus InterfaceQspi RAM 0x01 Receive RAMRelative Address Register 0x00 0x0FTransmit RAM Command RAMBaud Rate Selection System Clock Transfer DelaysQspiclk Frequency as Function of System Clock and Baud Rate 66.67 MHzTransfer Length Programming Model Qspi RegistersQMR Field Descriptions Qspi Mode Register QMR4gives QMR field descriptions Value Bits per transferQmrcpha = = Qdlyrqcd Qcrcont = = Qdlyrdtl Qspi Delay Register QdlyrQspics Qmrcpol = QCD6gives QWR field descriptions Qspi Wrap Register QWR5gives Qdlyr field descriptions Qdlyr Field DescriptionsQIR Field Descriptions Qspi Interrupt Register QIR7describes QIR fields Addr Qspi Address Register QARQspi Data Register QDR QCR0-QCR15 Field Descriptions Command RAM Registers QCR0-QCR158gives QCR field descriptions Qspiclk QS2 Qspidout QS3 Qspidin Programming ExampleQSPICS30 QS4 QS522-17 22-18 Uart Ucts Urts Urxd UtxdSerial Module Overview Ipsbar Offset 3124 2316 158 Register DescriptionsUart Module Memory Map Uart Mode Registers 1 UMR1n ERRUMR1n Field Descriptions Parity Mode Parity Type PT=2describes UMR1n fields CTSUMR2 n Field Descriptions Uart Mode Register 2 UMR2n3describes UMR2n fields UMR2n Field Descriptions Uart Status Registers USRn4describes USRn fields USRn Field DescriptionsRCS TCS Uart Clock Select Registers UCSRn5describes UCSRn fields RCS Uart Command Registers UCRnUCSRn Field Descriptions DtinBits Value Command Description UCR n Field DescriptionsUCRn Field Descriptions Uart Receive Buffers URBnUart Transmit Buffers UTBn Uipcr n Field Descriptions Uart Input Port Change Registers UIPCRn7describes UIPCRn fields COS CTSUart Interrupt Status/Mask Registers UISRn/UIMRn UACRs, shown in -7,control the input enableUart Auxiliary Control Register UACRn 8describes UACRn fieldsUisr n/UIMR n Field Descriptions Uart Baud Rate Generator Registers UBG1n/UBG2n9describes UISRn and UIMRn fields 10describes UIPn fields Uart Output Port Command Registers UOP1n/UOP0nUart Input Port Register UIPn 11describes UOP1 and UOP0 fields11. UOP1/UOP0 Field Descriptions Ucts Uart Module Signal DefinitionsIRQ Programmable Divider 12. Uart Module SignalsTransmitter/Receiver Clock Source System Clock Baud Rates Following sections describe how to calculate baud ratesCalculating Baud Rates SysclkTherefore UBG1n = 0x00 and UBG2n = 0xD6 Transmitter and Receiver Operating ModesTransmitter External Clock23-21 20. Transmitter Timing Diagram ReceiverFifo Stack 21shows receiver functional timing23-24 Looping Modes Automatic Echo ModeLocal Loop-Back Mode Multidrop Mode Remote Loop-Back Mode25. Multidrop Mode Timing Diagram Read Cycles Bus OperationProgramming Write CyclesInterrupt and DMA Request Initialization Setting up the Uart to Generate Core InterruptsSetting up the Uart to Request DMA Service 13. Uart Interrupts15shows the Uart module initialization sequence Register SettingUart Module Initialization Sequence 14. Uart DMA Requests26. Uart Mode Programming Flowchart Sheet 1 26. Uart Mode Programming Flowchart Sheet 2 26. Uart Mode Programming Flowchart Sheet 3 26. Uart Mode Programming Flowchart Sheet 4 26. Uart Mode Programming Flowchart Sheet 5 23-36 Interface Features Chapter I2C InterfaceIadr Acknowledge bit generation/detection Bus-busy detectionIfdr SCL SDA24.3 I2C System Configuration 24.4 I2C ProtocolArbitration Procedure Repeated StartClock Stretching Clock SynchronizationHandshaking SCL1 SCL2I2C Interface Memory Map 24.5.1 I2C Address Register I2ADR2describes I2ADR fields I2ADR Field DescriptionsI2FDR Field Descriptions 24.5.2 I2C Frequency Divider Register I2FDR3describes I2FDRIC DividerI2CR Field Descriptions 24.5.3 I2C Control Register I2CR4describes I2CR fields IEN IienI2SR Field Descriptions 24.5.4 I2C Status Register I2SR5describes I2SR fields ICF Iaas IBB IAL SRW IIF24.6 I2C Programming Examples 24.5.5 I2C Data I/O Register I2DRGeneration of Start Post-Transfer Software Response24.6.4 Generation of Stop I2SRSlave Mode Generation of Repeated StartArbitration Lost SRW=1 RXAK=IAAS=1 Write24-16 Chapter FlexCAN RAM MB3 MB2 MB1 MB0 Cantx CanrxFlexCAN Memory Map 25.1.2 External SignalsFlexCAN Memory Map Message Buffer Structure Can SystemMessage Buffers Typical can system is shown below in FigureCommon Fields for Extended and Standard Format Frames Message Buffer Codes for Transmit Buffers Common Extended/Standard Format FramesMessage Buffer Codes for Receive Buffers Fields for Standard Format Frames Message Buffer Memory MapFields for Extended Format Frames Extended Format FramesIdhigh Idlow Functional OverviewMessage Buffers Transmit Process Receive ProcessMessage Buffer Handling Self-Received FramesReceive Message Buffer Deactivation Serial Message Buffers SMBsTransmit Message Buffer Deactivation Remote Frames Locking and Releasing Message BuffersTime Stamp Listen-Only ModeOverload Frames Examples of System Clock/CAN Bit-Rate/S-Clock Configuring the FlexCAN Bit TimingBit Timing Freq Mhz Time-quanta/bit Value +FlexCAN Error Counters FlexCAN Initialization Sequence Special Operating Modes Debug ModeLow-Power Stop Mode for Power Saving Canmcr Auto-Power Save Mode Interrupts8describes the Canmcr fields Can Module Configuration Register CanmcrProgrammer’s Model Stop FRZ Halt Notrdy Wakemsk Softrst FrzackCanmcr Field Descriptions StopFlexCAN Control Register 0 CANCTRL0 9describes the CANCTRL0 fieldsFlexCAN Control Register 1 CANCTRL1 10. Transmit Pin ConfigurationTransmit Pin Configuration 11describes the CANCTRL1 fields11. CANCTRL1 Field Descriptions Prescaler Divide Register Presdiv12describes the Presdiv fields Samp12. Presdiv Field Descriptions FlexCAN Control Register 2 CANCTRL213describes the CANCTRL2 fields 13. CANCTRL2 Field Descriptions14. Timer Field Descriptions Free Running Timer Timer14describes the Timer fields Rx Mask RegistersReceive Mask Registers RXGMASK, RX14MASK, RX15MASK 12. Rx Mask Registers RXGMASK, RX14MASK, and RX15MASK16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions FlexCAN Error and Status Register Estat17describes the Estat fields 17. Estat Field Descriptions BiterrBUF15M BUF14M BUF13M Interrupt Mask Register Imask18describes the Imask fields BUF10M BUF9M BUF8M18. Imask Field Descriptions Interrupt Flag Register Iflag19describes the Iflag fields 19. Iflag Field Descriptions20describes the Rxectr fields FlexCAN Receive Error Counter RxectrFlexCAN Transmit Error Counter Txectr 21describes the Txectr fieldsChapter General Purpose I/O Module MCF5282 Ports Module Block Diagram Overview FeaturesSdram control Bit DMA timers Uart transmit/receive Modes of OperationExternal Signal Description MCF5282 Ports External SignalsSCL ErxerSDA UCTS0Register Overview 31-24 23-16 15-8 AccessMemory Map/Register Definition MCF5282 Ports Module Memory MapClra Clrb Clrc Clrd Ddrb DdrcDdreh Ddrel Clre Clrf Clrg ClrhPort Output Data Registers PORTn Port Output Data Registers 8-bitPORTn 8-bit, 7-bit, 6-bit, and 4-bit Field Descriptions Port Data Direction Registers DDRnPORTn bits are described in Table Register Bits Name DescriptionPort Data Direction Register 7-bit Port Pin Data/Set Data Registers PORTnP/SETn 10. Port Pin Data/Set Data Registers 8-bitPORTnP/SETn 8-bit, 6-bit, and 4-bit Field Descriptions Port Clear Output Data Registers CLRnPORTnP/SETn bits are described in Table PORTUAP/SETUACLRn register bits are described in Table CLRn 8-bit,7-bit, 6-bit, and 4-bit Field DescriptionsExternal Boot Reset Values for Pbcdpar BitsPort Size Pbpa Reset Pcdpa Reset Port B/C/D Pin Assignment Register PbcdparPEPA3 Port E Pin Assignment Register PeparPepar Field Descriptions 10. Reset Values for Pepar Bits and Fields Single chip mode11. Pfpar Field Descriptions Port F Pin Assignment Register PfparPfpar controls the pin function of port F75 12. Pjpar Field Descriptions Port J Pin Assignment Register PjparPjpar controls the pin function of port J Psdpar controls the pin function of port SD Port SD Pin Assignment Register PsdparPort AS Pin Assignment Register Paspar Paspar controls the pin function of port ASPort EH/EL Pin Assignment Register Pehlpar 14. Paspar Field Descriptions15. Pehlpar Field Descriptions Port QS Pin Assignment Register PqsparPqspar controls the pin function of port QS ECOL, ERXCLK, ERXDV, ERXD0, EcrsPTCPA3 PTCPA2 PTCPA1 PTCPA0 Port TC Pin Assignment Register PtcparPtcpar controls the pin function of port TC PTDPA3 PTDPA2 PTDPA1 PTDPA0 Port TD Pin Assignment Register PtdparPtdpar controls the pin function of port TD Port UA Pin Assignment Register Puapar Puapar controls the pin function of port UAPort Digital I/O Timing Clkout Input PIN Register PIN DataInitialization/Application Information Clkout Output Data Register Output PINChapter Queued Analog-to-Digital Converter Qadc Qadc Block Diagram Debug Mode Modes of OperationPort QA Signal Functions Port QA Analog Input SignalsPort QB Analog Input Signals Port QB Signal FunctionsPort QA Digital Input/Output Signals Multiplexed Analog Input Signals External Trigger Input SignalsMultiplexed Address Output Signals Port QB Digital I/O SignalsDedicated Digital I/O Port Supply Signal Voltage Reference SignalsDedicated Analog Supply Signals Multiplexed Analog Input ChannelsQadc Memory Map Qadc Module Configuration Register QadcmcrThis subsection describes the Qadc registers Qadc Test Register Qadctest Port Data Registers Portqa and PortqbPort QA and QB Data Direction Register Ddrqa and Ddrqb ANZ ANY ANX ANWThis subsection describes the Qadc control registers Control RegistersQadc Control Register 0 QACR0 Qadc Control Register 0 QACR0 QACR0 Field Descriptions QPR6Divisor Prescaler fSYS Divide-by ValuesQPR60 CIE1 Qadc Control Register 1 QACR1CIE1 PIE1 SSE1 Operating Mode Queue 1 Operating ModesQadc Control Register 2 QACR2 CIE2 PIE2 SSE2 ResumeCIE2 QACR2 Field DescriptionsQueue 2 Operating Modes BQ2This subsection describes the Qadc status registers Status RegistersQadc Status Register 0 QASR0 MQ2128 Operating Modes27-20 Queued Analog-to-Digital Converter Qadc 27-21 QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0 CF1 PF1 CF2QS9 QS8 11. CCW Pause Bit Response Scan Mode Queue Operation PF Asserts?10. QASR0 Field Descriptions CWP12. Queue Status Queue 1/Queue 2 States12. Queue Status Transition Conversion Command Word Table CCW Qadc Status Register 1 QASR1BYP IST1 IST015. Input Sample Times Non-Multiplexed Input Signals Channel NumberPort Signal Name IST10 Input Sample TimesResult Registers 17. Multiplexed Channel Assignments and Signal DesignationsMultiplexed Input Signals Channel Number Right-Justified Unsigned Result Register Rjurr18. Rjurr Field Descriptions Left-Justified Signed Result Register LjsrrLeft-Justified Unsigned Result Register Ljurr ResultExternal Multiplexing 27.7 Functional DescriptionResult Coherency External Multiplexing Operation 18. External Multiplexing Configuration Analog-to-Digital Converter Operation Analog SubsystemModule Version Options 21. Analog Input Channels19. Qadc Analog Subsystem Block Diagram Conversion Cycle TimesChannel Decode and Multiplexer Sample BufferBias Digital Control SubsystemComparator Successive Approximation Register SARQueue Priority Timing Examples Queue Priority22. Qadc Queue Operation with Pause 23. Status Bits Queue Priority Schemes22. Trigger Events Events23. CCW Priority Situation 24. CCW Priority Situation 26. CCW Priority Situation 28. CCW Priority Situation 30. CCW Priority Situation 32. CCW Priority Situation 34. CCW Freeze Situation 38. CCW Freeze Situation Boundary Conditions Scan Modes Disabled ModeReserved Mode Single-Scan ModesSoftware-Initiated Single-Scan Mode Externally Triggered Single-Scan Mode Externally Gated Single-Scan ModeInterval Timer Single-Scan Mode Continuous-Scan Modes Software-Initiated Continuous-Scan Mode Externally Triggered Continuous-Scan Mode Externally Gated Continuous-Scan ModePeriodic Timer Continuous-Scan Mode Qadc Clock Qclk GenerationPeriodic/Interval Timer 42. Qadc Clock Subsystem FunctionsConversion Command Word Table 43illustrates the operation of the queue structure43. Qadc Conversion Queue Operation Queued Analog-to-Digital Converter Qadc 27-61 Signal Connection Considerations Result Word TableAnalog Reference Signals Analog Power Signals45. Errors Resulting from Clipping Conversion Timing Schemes46. External Positive Edge Trigger Mode Timing with Pause 47. Gated Mode, Single Scan Timing Analog Supply Filtering and Grounding 48. Gated Mode, Continuous Scan Timing49. Star-Ground at the Point of Power Supply Origin 50. Input Signal Subjected to Negative Stress Accommodating Positive/Negative Stress ConditionsIinjn IinjpAnalog Input Considerations 52. External Multiplexing of Analog Signal Sources Analog Input Pins 53. Electrical Model of an A/D Input SignalSource Resistance RF + Rsrc 100 Ω 10 kΩ 100 kΩ Settling Time for the External Circuit24. External Circuit Settling Time to 1/2 LSB Interrupt Operation Error Resulting from Leakage25. Error Resulting from Input Leakage IOff Queue Queue Activity Status Interrupt Flag Interrupt Sources26. Qadc Status Flags and Interrupt Sources PF1 PIE1Chapter Reset Controller Module Rsto Reset Controller Signal PropertiesRsti Name Direction InputReset Control Register RCR Reset Controller Memory MapLvdie Reset Status Register RSRLvdf Soft WDR PORRSR Field Descriptions WDRReset Source Summary Reset SourcesPower-On Reset Source TypeLoss-of-Clock Reset External ResetWatchdog Timer Reset Loss-of-Lock ResetReset Control Flow Reset Control Flow Internal Reset Request Concurrent ResetsSynchronous Reset Requests Power-On Reset/Low-Voltage Detect ResetReset Status Flags 28-12 Debug module is shown in Figure Processor/Debug Module InterfaceSignal Description Debug Module SignalsPST30 Definition Hex Real-Time Trace SupportProcessor Status Encoding Begin Execution of Taken Branch PST = PST30 Definition Hex BinaryClkout PST DdataAbhr AatrAblr CSRRev. a Shared BDM/Breakpoint Hardware Revision a Shared Debug ResourcesBDM/Breakpoint Registers DRc4-0 Register Name Abbreviation Initial StateAatr Field Descriptions Address Attribute Trigger Register Aatr5describes Aatr fields TMMAddress Breakpoint Registers ABLR, Abhr Address Breakpoint Registers ABLR, Abhr7describes Abhr fields Configuration/Status Register CSR6describes Ablr fields Ablr Field Description8describes CSR fields CSR Field DescriptionsData Breakpoint/Mask Registers DBR, Dbmr IPI10describes Dbmr fields Program Counter Breakpoint/Mask Registers PBR, Pbmr9describes DBR fields 13describes Pbmr fields Trigger Definition Register TDR12describes PBR fields 12. PBR Field Descriptions14describes TDR fields 14. TDR Field DescriptionsEdum Background Debug Mode BDMCPU Halt Eduu29-17 DSO BDM Serial InterfaceClkout Dsclk DSI 15describes receive BDM packet fields Receive Packet FormatTransmit Packet Format 16describes transmit BDM packet fieldsSection Command BDM Command Set17. BDM Command Summary Extension Words as Required ColdFire BDM Command Format18describes BDM fields 18. BDM Field DescriptionsCommand Sequence Diagrams 16. Command Sequence DiagramRead A/D Register RAREG/RDREG Command Set DescriptionsCommand Sequence Write A/D Register WAREG/WDREG Read Memory Location Read21. Read Command/Result Formats 22. Read Command Sequence23. Write Command Format Write Memory Location WriteDump Memory Block Dump Set is returned if a bus error occursOperands are sent as 16 and 32 bits, respectively 25. Dump Command/Result Formats 26. Dump Command Sequence Fill Memory Block Fill27. Fill Command Format 28. Fill Command SequenceResume Execution GO No Operation NOP19. Control Register Map Read Control Register RcregRc encoding BDM Accesses of the Stack Pointer Registers A7 SSP, USP BDM Accesses of the Emac Registers35. Wcreg Command/Result Formats Write Control Register WcregRead Debug Module Register Rdmreg 20shows the definition of DRc encodingDRc40 Debug Register Definition Mnemonic Initial State Write Debug Module Register Wdmreg20. Definition of DRc Encoding-Read 21. DDATA30/CSRBSTAT Breakpoint Response Real-Time Debug SupportTheory of Operation Breakpoint StatusEmulator Mode Concurrent BDM and Processor Operation User Instruction Set 22. PST/DDATA Specification for User-Mode InstructionsProcessor Status, Ddata Definition Instruction Operand Syntax29-41 29-42 23. PST/DDATA Specification for MAC Instructions 24. PST/DDATA Specification for Supervisor-Mode Instructions Supervisor Instruction SetGND Dsclk Reset DSIMotorola-Recommended BDM Pinout GND PST3 PST2 PST1 PST0 DDATA3 DDATA2 DDATA1 DDATA029-46 Chapter Chip Configuration Module CCM Single-Chip Mode Chip Configuration Module Block Diagram1provides an overview of the CCM signals Signal Descriptions30.4.3 D2624, 21, 1916 Reset Configuration Override RconWrite-Once Bits Read/Write Accessibility Configuration Read/Write AccessSzen Chip Configuration Register CCRFollowing subsection describes the CCM registers BMTRcsc Rpllsel Rpllref Reset Configuration Register RconBootps RcscChip Select Configuration Rcsc Chip Select ConfigurationBootps Port Size Configuration Boot Port SizePIN PRN Reset ConfigurationChip Identification Register CIR Reset Configuration Pin States During Reset 10. Configuration During ResetD2524 Chip Mode SelectionClock Mode Clock Mode Selection Boot Device SelectionOutput Pad Strength Configuration 11. Chip Configuration Mode SelectionCCM does not generate interrupt requests Chip Select Configuration13. Clock Mode Selection Chapter Ieee 1149.1 Test Access Port Jtag Jtag Block Diagram Jtagen Jtag Enable External Signal Description31.3.1 Detailed Signal Description Pin Function SelectedSignal State to the Disable Module 31.3.1.3 TMS/BKPT Test Mode Select / BreakpointTRST/DSCLK Test Reset / Development Serial Clock Tclk Test Clock InputInstruction Shift Register IR Memory Map/Register DefinitionMemory Map Idcode RegisterTestctrl Register Bypass RegisterJtagcfmclkdiv Register Boundary Scan RegisterJtag Module TAP ControllerJtag Instructions Jtag Instructions5describes public and private instructions Instruction IR30 Instruction SummarySAMPLE/PRELOAD Instruction External Test Instruction ExtestIdcode Instruction Testleakage Instruction Enabletestctrl InstructionLockoutrecovery Instruction Highz InstructionClamp Instruction Initialization/Application InformationRestrictions Bypass InstructionNonscan Chain Operation Chapter Mechanical Data Pinout MCF5282 Pinout 256 MapbgaSecondary Tertiary MCF5282 Signal Description by Pin NumberMapbga Pin Pin Functions PG2 PG4PG3 PF4GPTA0 PUA1 VDDGPTB0 PQA3 ETRIG1 VRH VDD Vssa VSSGPTB2 PQA0 MA0 VDD VddaPUA3 VSS Xtal Jtagen PQS5Orderable Part Numbers Motorola Part Description Speed TemperatureOrdering Information 32-8 Absolute Maximum Ratings1 Rating Symbol Value UnitMaximum Ratings Rating Symbol HBMCharacteristic Symbol Value Unit Thermal CharacteristicsThermal Characteristics 2lists thermal resistance valuesCharacteristic Symbol Min Max Unit DC Electrical SpecificationsDC Electrical Specifications1 Solving equations 1 and 2 for K givesWait Doze Stop Phase Lock Loop Electrical Specifications PLL Electrical SpecificationsParameter Symbol Min Max Unit Qadc Electrical CharacteristicsQadc Electrical Specifications Operating Qadc Absolute Maximum RatingsParameter Symbol Min IOH = TBDSgfm Flash Program and Erase Characteristics Flash Memory CharacteristicsQadc Conversion Specifications Operating Num Parameter Symbol Min Max Unit10. Processor Bus Input Timing Specifications External Interface Timing CharacteristicsSgfm Flash Module Life Characteristics Name Characteristic Symbol Min Max Unit Control Outputs Processor Bus Output Timing Specifications11. External Bus Output Timing Specifications Timings listed in -10are shown in FigureData Outputs Read/Write Internally Terminated Timing Read Bus Cycle Terminated by TA Read Bus Cycle Terminated by TEA Symbol Min Max Unit Sras Scas DramwSras SCAS1 Dramw 33.9 General Purpose I/O Timing13. Gpio Timing1 Reset and Configuration Override Timing 14. Reset and Configuration Override TimingNum Characteristic Min Max Units 33.11 I2C Input/Output Timing Specifications15. I2C Input Timing Specifications between SCL and SDA Clkout Rsti RstoFast Ethernet AC Timing Specifications 16. I2C Output Timing Specifications between SCL and SDA17. MII Receive Signal Timing MII Receive Signal Timing ERXD30, ERXDV, ERXER, and ErxclkMII Transmit Signal Timing ETXD30, ETXEN, ETXER, Etxclk Num Characteristic Min Max Unit18. MII Transmit Signal Timing MII Async Inputs Signal Timing Ecrs and Ecol19lists MII asynchronous inputs signal timing 19. MII Async Inputs Signal TimingMII Serial Management Channel Timing Emdio and Emdc 20. MII Serial Management Channel Timing21lists timer module AC timings DMA Timer Module AC Timing SpecificationsQspi Electrical Specifications 22lists Qspi timingsJtag and Boundary Scan Timing 23. Jtag and Boundary Scan Timing17. Test Access Port Timing 16. Boundary Scan Jtag TimingClkout VIL Debug AC Timing Specifications24. Debug AC Timing Specification 20shows real-time trace timing for the values in Table 20. Real-Time Trace AC TimingACR0 Table A-1. CPU Space Register Memory MapAddress Name Mnemonic Size ACR1I2C Table A-2. Module Memory Map OverviewAddress Module Size QadcSdramc Registers Table A-3. Register Memory MapAddress Name Mnemonic Size SCM Registers Chip Select RegistersDMA Registers Uart Registers UBG21 UISR1UIMR1 UIP01Qspi Registers DMA Timer RegistersI2C Registers Interrupt Controller Ipsbar + 0xC56 IPRL1 SWACKR0IPRH1 IMRH1Global Interrupt Acknowledge Cycle Registers FEC RegistersGpio Registers Portsd PortasPortqs PorttcPortbp PortapSeta Ipsbar + Setb Ipsbar +Clrg ClraClrf ClrasClock Module Registers Edge Port RegistersWatchdog Timer Registers General Purpose Timer a Registers Qadc RegistersGeneral Purpose Timer B Registers FlexCAN Registers Flash Registers MCF5282 User’s Manual Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14 Index-15 Index-16