Motorola MCF5281, MCF5282 user manual Fifo Stack, 21shows receiver functional timing

Operation

After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a non-zero character is received without a stop bit (framing error) and URXD remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit were detected. Parity error, framing error, overrun error, and received break conditions set the respective PE, FE, OE, RB error and break flags in the USRn at the received character boundary and are valid only if USRn[RxRDY] is set.

If a break condition is detected (URXD is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register and USRn[RB,RxRDY] are set. URXD must return to a high condition for at least one-half bit time before a search for the next start bit begins.

The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. If the break begins in the middle of a character, the receiver places the damaged character in the Rx FIFO stack and sets the corresponding USRn error bits and USRn[RxRDY]. Then, if the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RxRDY].

Figure 23-21shows receiver functional timing.

UTXDn

Receiver

Enabled

USRn[RxRDY]

USRn[FFULL]

internal module select

Overrun

USRn[OE]

URTSn4

C1 C2 C3 C4 C5 C6 C7 C8

C6, C7, and C8 will be lost

Status		Status	Status	Status
Data	C5 will	Data	Data	Data
(C1)		(C2)	(C3)	(C4)
	be lost

Reset by

command

Manually asserted first time,	Automatically asserted
automatically negated if overrun occurs	when ready to receive

UOP0[RTS] = 1

Figure 23-21. Receiver Timing

23.5.2.3FIFO Stack

The FIFO stack is used in the UART’s receive buffer logic. The stack consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the URXD (see Figure 23-19). Data is assembled in the receiver shift

MOTOROLA Chapter 23. UART Modules 23-23