ILLUSTRATIONS

Figure

Title

Page

Number

Number

 

20-6

GPT Counter Register (GPTCNT)

20-7

20-7

GPT System Control Register 1 (GPTSCR1)

20-8

20-8

Fast Clear Flag Logic

20-9

20-9

GPT Toggle-On-Overflow Register (GPTTOV)

20-9

20-10

GPT Control Register 1 (GPTCTL1)

20-9

20-11

GPT Control Register 2 (GPTCTL2)

20-10

20-12

GPT Interrupt Enable Register (GPTIE)

20-10

20-13

GPT System Control Register 2 (GPTSCR2)

20-11

20-14

GPT Flag Register 1 (GPTFLG1)

20-12

20-15

GPT Flag Register 2 (GPTFLG2)

20-12

20-16

GPT Channel[0:3] Register (GPTCn)

20-13

20-17

Pulse Accumulator Control Register (GPTPACTL)

20-13

20-18

Pulse Accumulator Flag Register (GPTPAFLG)

20-14

20-19

Pulse Accumulator Counter Register (GPTPACNT)

20-15

20-20

GPT Port Data Register (GPTPORT)

20-16

20-21

GPT Port Data Direction Register (GPTDDR)

20-16

20-22

Channel 3 Output Compare/Pulse Accumulator Logic

20-19

21-1

DMA Timer Block Diagram

21-2

21-2

DTMRn Bit Definitions

21-4

21-3

DTXMRn Bit Definitions

21-5

21-4

DTERn Bit Definitions

21-6

21-5

DTRRn Bit Definitions

21-7

21-6

DTCRn Bit Definitions

21-8

21-7

DTCNn Bit Definitions

21-8

22-1

QSPI Block Diagram

22-2

22-2

QSPI RAM Model

22-5

22-3

QSPI Mode Register (QMR)

22-10

22-4

QSPI Clocking and Data Transfer Example

22-11

22-5

QSPI Delay Register (QDLYR)

22-11

22-6

QSPI Wrap Register (QWR)

22-12

22-7

QSPI Interrupt Register (QIR)

22-13

22-8

QSPI Address Register

22-14

22-9

QSPI Data Register (QDR)

22-14

22-10

Command RAM Registers (QCR0–QCR15)

22-15

22-11

QSPI Timing

22-16

23-1

Simplified Block Diagram

23-1

23-2

UART Mode Registers 1 (UMR1n)

23-4

23-3

UART Mode Register 2 (UMR2n)

23-6

23-4

UART Status Register (USRn)

23-7

23-5

UART Clock Select Register (UCSRn)

23-8

23-6

UART Command Register (UCRn)

23-9

23-7

UART Receive Buffer (URBn)

23-11

23-8

UART Transmit Buffer (UTBn)

23-12

 

 

 

MOTOROLA

Illustrations

xxvii

Page 27
Image 27
Motorola MCF5281, MCF5282 user manual 20-20