Motorola MCF5282, MCF5281 user manual Signal Description, Debug Module Signals

Signal Description

systems can access saved data because the hardware supports concurrent operation of the processor and BDM-initiated commands. See Section 29.6, “Real-Time Debug Support.”

NOTE

Enabling Flash security will disable BDM communications.

29.2 Signal Description

Table 29-1describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor’s clock signal. The standard 26-pin debug connector is shown in Section 29.8, “Motorola-Recommended BDM Pinout.”

		Table 29-1. Debug Module Signals
Signal		Description
Development Serial		Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two
Clock (DSCLK)		consecutive rising CLKOUT edges.) Clocks the serial communication port to the debug module during
		packet transfers. Maximum frequency is 1/5 the processor status clock (CLKOUT) speed. At the
		synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.
Development Serial		Internally synchronized input that provides data input for the serial communication port to the debug
Input (DSI)		module.
Development Serial		Provides serial output communication for debug module responses. DSO is registered internally.
Output (DSO)
Breakpoint		Input used to request a manual breakpoint. Assertion of		puts the processor into a halted state after
	(BKPT)		BKPT
		the current instruction completes. Halt status is reflected on processor status signals (PST[3:0]) as the
		value 0xF.
CLKOUT		See Figure 29-2.CLKOUT indicates when the development system should sample PST and DDATA
		values.
Debug Data		These output signals display the register breakpoint status as a default, or optionally, captured address
(DDATA[3:0])		and operand values. The capturing of data values is controlled by the setting of the CSR. Additionally,
		execution of the WDDATA instruction by the processor captures operands which are displayed on
		DDATA. These signals are updated each processor cycle.
Processor Status		These output signals report the processor status. Table 29-2shows the encoding of these signals. These
(PST[3:0])		outputs indicate the current status of the processor pipeline and, as a result, are not related to the current
		bus transfer. The PST value is updated each processor cycle.

Figure 29-2shows CLKOUT timing with respect to PST and DDATA.

CLKOUT

PST or DDATA

Figure 29-2. CLKOUT Timing

29-2 MCF5282 User’s Manual MOTOROLA