Motorola MCF5282, MCF5281 user manual BDM Command Set, BDM Command Summary, Section Command

Background Debug Mode (BDM)

29.5.3 BDM Command Set

Table 29-17summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior.

Table 29-17. BDM Command Summary

Command	Mnemonic	Description	CPU	Section	Command
			State 1		(Hex)
Read A/D	RAREG/	Read the selected address or data register and return the	Halted	29.5.3.3.1	0x218 {A/D,
register	RDREG	results through the serial interface.			Reg[2:0]}
Write A/D	WAREG/	Write the data operand to the specified address or data	Halted	29.5.3.3.2	0x208 {A/D,
register	WDREG	register.			Reg[2:0]}
Read memory	READ	Read the data at the memory location specified by the	Steal	29.5.3.3.3	0x1900—byte
location		longword address.			0x1940—word
					0x1980—lword
Write memory	WRITE	Write the operand data to the memory location specified	Steal	29.5.3.3.4	0x1800—byte
location		by the longword address.			0x1840—word
					0x1880—lword
Dump	DUMP	Used with READ to dump large blocks of memory. An	Steal	29.5.3.3.5	0x1D00—byte
memory block		initial READ is executed to set up the starting address of			0x1D40—word
		the block and to retrieve the first result. A DUMP			0x1D80—lword
		command retrieves subsequent operands.
Fill memory	FILL	Used with WRITE to fill large blocks of memory. An	Steal	29.5.3.3.6	0x1C00—byte
block		initial WRITE is executed to set up the starting address of			0x1C40—word
		the block and to supply the first operand. A FILL			0x1C80—lword
		command writes subsequent operands.
Resume	GO	The pipeline is flushed and refilled before resuming	Halted	29.5.3.3.7	0x0C00
execution		instruction execution at the current PC.
No operation	NOP	Perform no operation; may be used as a null command.	Parallel	29.5.3.3.8	0x0000
Read control	RCREG	Read the system control register.	Halted	29.5.3.3.9	0x2980
register
Write control	WCREG	Write the operand data to the system control register.	Halted	29.5.3.3.10	0x2880
register
Read debug	RDMREG	Read the debug module register.	Parallel	29.5.3.3.11	0x2D {0x4 2
module					DRc[4:0]}
register
Write debug	WDMREG	Write the operand data to the debug module register.	Parallel	29.5.3.3.12	0x2C {0x42
module					DRc[4:0]}
register

1General command effect and/or requirements on CPU operation:

-Halted. The CPU must be halted to perform this command.

-Steal. Command generates bus cycles that can be interleaved with bus accesses.

-Parallel. Command is executed in parallel with CPU activity.

20x4 is a three-bit field.

Unassigned command opcodes are reserved by Motorola. All unused command formats within any revision level perform a NOP and return the illegal command response.

29-20 MCF5282 User’s Manual MOTOROLA