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Motorola MCF5282, MCF5281 user manual Read Bus Cycle Terminated by TA

Models: MCF5282 MCF5281

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Processor Bus Output Timing Specifications

	S0	S1	S2	S3	S4	S5	S0	S1
CLKOUT
CSn	B6a			B7a
CSn				B7a
A[23:0]	B8					B9
A[23:0]
SIZ[1:0]
TS	B8
TS		B9
TIP	B8					B9
						B9

OE	B6c
OE				B7
				B7
R/W (H)
BS[3:0]				B7
BS[3:0]
						B5
			B4
D[31:0]
TA
TEA (H)

Figure 33-3. Read Bus Cycle Terminated by TA

Figure 33-4shows a bus cycle terminated by TEA; it displays the timings listed in Table 33-11.

33-14

MCF5282 User’s Manual

MOTOROLA

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Motorola MCF5282, MCF5281 user manual Read Bus Cycle Terminated by TA

Contents

MCF5282 ColdFire Microcontroller User’s Manual HOW to Reach US USA/EUROPE/LOCATIONS not Listed IND IND Contents Chapter Enhanced Multiply-Accumulate Unit Emac Timing Assumptions Move Instruction Execution TimesColdFire Flash Module CFM Chapter CacheChapter Static RAM Sram Chapter Power Management Chapter System Control Module SCMClock Module Interrupt Controller ModulesSignal Descriptions Chapter Edge Port Module EportChapter Chip Select Module Chapter External Interface Module EIMChapter Synchronous Dram Controller Module Chapter DMA Controller ModuleChapter Fast Ethernet Controller FEC Chapter General Purpose Timer Modules Gpta and Gptb Chapter Watchdog Timer ModuleChapter Programmable Interrupt Timer Modules PIT0-PIT3 20.3 Chapter DMA Timers DTIM0-DTIM3 Chapter Queued Serial Peripheral Interface Qspi ModuleChapter Uart Modules Chapter I2C InterfaceChapter FlexCAN Chapter General Purpose I/O Module Chapter Queued Analog-to-Digital Converter Qadc27.4.7 Reset Controller Module Chapter Debug SupportChapter Chip Configuration Module CCM Chapter Ieee 1149.1 Test Access Port JtagElectrical Characteristics Chapter Mechanical DataAppendix a Register Memory Map Paragraph Title Number 31.6.2 Nonscan Chain Operation 31-12Illustrations Title Number10-7 13-4 17-13 20-20 23-10 25-31 Qadc Status Register 0 QASR0 27-22 27-12 27-53 29-39WDMREG BDM Command Format 29-36 29-40 Tables Charge Pump Current and MFD in Normal Mode Operation 10-13 15-18 17-30 20-23 25-21 27-13 29-43 33-21 Timer Module AC Timing Specifications 33-24 33-22 Audience OrganizationOrganization Xlv ColdFire Documentation Suggested ReadingGeneral Information Conventions Meaning Acronyms and AbbreviationsTable i. Acronyms and Abbreviated Terms Terminology Conventions Table ii. Notational ConventionsOperand Syntax Opcode WildcardACC CCRPort Name PSTLSW MSWRevision History Table iii provides a revision history for this documentTable iii. Revision History SSTFrsr Revision Date Substantive ChangesNumber Release Liv 10.3.6/10-11 RAMBAR.’Revision Number Substantive Changes Section/PageMCF5282 Key Features Chapter OverviewMCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Block Diagram Cache Configuration Configuration Tag Address Data Array AddressVersion 2 ColdFire Core CacheDebug Module SramFlash System Control Module External Interface Module EIMPower Management Chip SelectGeneral Input/Output Ports Interrupt Controllers INTC0/INTC1Test Access Port Uart ModulesPeriodic Interrupt Timers PIT0-PIT3 DMA Timers DTIM0-DTIM3General-Purpose Timers GPTA/GPTB Software Watchdog Timer Phase Locked Loop PLLReset DMA ControllerMCF5282-Specific Features MCF5282-Specific Features Processor Pipelines IAGFifo DsocProcessor Register Description User Programming ModelData Registers D0-D7 Address Registers A0-A6Stack Pointer A7 Program Counter PCCondition Code Register CCR Bits Name DescriptionEmac Programming Model Supervisor Programming ModelBits Status Register SRSystem Byte Condition Code Register CCR Supervisor/User Stack Pointers A7 and OTHERA7 Access Control Registers ACR0, ACR1 Programming ModelVector Base Register VBR Cache Control Register CacrLocal Memory Registers Additions to the Instruction Set ArchitectureName CPU Space Rc Written with Register Name Instruction Description Exception Processing OverviewISA Revision A+ New Instructions Exception Vector Assignments Vector Stacked Program Assignment NumberS Offset Hex Counter0x100-0x3FC Next Exception Stack Frame DefinitionFormat Field Encodings Access Error Exception Fault Status EncodingsProcessor Exceptions FS30 DefinitionAddress Error Exception Illegal Instruction ExceptionDivide-By-Zero Privilege ViolationDebug Interrupt Unimplemented Line-A OpcodeUnimplemented Line-F Opcode RTE and Format Error Exception Fault-on-Fault HaltReset Exception Trap Instruction ExceptionVER REV MAC DIV Emac FPU MMU ISA DebugMAC D0 Hardware Configuration Info Field DescriptionVER ICA ICA Icsiz RAM0SIZ ROM0SIZBusw DCA Dcsiz RAM1SIZ ROM1SIZ 4KB RAM 8KB RAM16KB RAM 32KB RAMInstruction Execution Timing Timing AssumptionsAddress10 Size Kbus Additional Operations CR/W Move Instruction Execution Times10. Misaligned Operand References Source Destination Ax+ D16,Ax D8,Ax,Xi Xxx.wl 11. Move Byte and Word Execution Times12. Move Long Execution Times Standard One Operand Instruction Execution Times Standard Two Operand Instruction Execution Times13. One Operand Instruction Execution Times 14. Two Operand Instruction Execution TimesStandard Two Operand Instruction Execution Times Miscellaneous Instruction Execution Times 15. Miscellaneous Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl D16,PC D8,PC,Xn*SFEffective Address Opcode An+ D16,An D8,An,X Xxx.wl #xxx Emac Instruction Execution Times16. Emac Instruction Execution Times Branch Instruction Execution Times ColdFire Instruction Set Architecture Enhancements17. General Branch Instruction Execution Times 18. BRA, Bcc Instruction Execution TimesOperation Assembler SyntaxAttributes Instruction FormatCondition Codes Byte Reverse Register ByterevAssembler Syntax BYTEREV.L Dx Attributes Find First One in Register Old Dx310 New Dx310Assembler SyntaxSTRLDSR #data Store/Load Status Register StrldsrSupported Starting with ISA A+ Chapter Enhanced Multiply-Accumulate Unit Emac Multiply-Accumulate UnitMultiply-Accumulate Functionality Diagram Introduction to the MACGeneral Operation Infinite Impulse Response IIR FilterFractional Alignment Motorola 1describes Macsr fields Memory Map/Register SetMAC Status Register Macsr Macsr Field Descriptions Fractional Operation Mode RoundingSummary of S/U, F/I, and R/T Control Bits Operational ModesSaving and Restoring the Emac Programming Model MULS/MULU Following code performs the Emac state restoreMask Register Mask MAC.sz Ry,RxSF,eay&,Rw Command Mnemonic Description Emac Instruction Set SummaryEmac Instruction Execution Times 3summarizes Emac unit instructionsAccumulator Mac Old Mov New Data RepresentationMac Mov MAC Opcodes Two’s Complement, Signed Fractional EquationMACSR.V = Emac Instruction Set Summary MACSR.Z = Emac Instruction Set Summary Motorola Emac Instruction Set Summary MCF5282 User’s Manual This chapter describes the MCF5282 cache operation Cache FeaturesCache Physical Organization Cache Physical Organization Cache Operation Interaction with Other ModulesMemory Reference Attributes Cache Coherency and InvalidationCLNF10 Longword Address Bits Cache Miss Fetch Algorithm/Line FillsInitial Fetch Offset vs. Clnf Bits Instruction Cache Operation as Defined by CACR31 CACR31 CACR10 Type of Instruction Fetch DescriptionCache Programming Model Cache Registers Memory MapCache Registers Cache Control Register CacrCenb CPD Cinv Didi Disd Invi InvdCeib DCM Dbwe DWP Eusp Clnf CenbCeib Cache Configuration as Defined by CACR31, 23 CACR31 CACR23 CACR22 Configuration DescriptionCACR23 CACR22 CACR21 CACR20 Configuration Operation Cache Invalidate All as Defined by CACR23, 22, 21Bufw Access Control Registers ACR0, ACR1External Fetch Size Based on Miss Address and Clnf BWE Between the processors local bus and the external busSram Programming Model Sram FeaturesSram Operation Sram Base Address Register Rambar PRI1 PRI2 SPVPRI1, PRI2 PRI12 Upper Bank Lower Bank PrioritySram Initialization Sram Base Address RegisterPower Management Typical Rambar Setting ExamplesSram Initialization Code Following loop initializes the entire Sram to zeroSram Programming Model Sram Programming Model MCF5282 User’s Manual Features Chapter ColdFire Flash Module CFMBlock Diagram CFM Block Diagram Memory Map CFM Array Memory MapCFM Configuration Field CFM Configuration FieldFlash Base Address Register Flashbar Address Offset from array base Size DescriptionMemory Map BA30 BA29 CFM Configuration Register Cfmcr CFM RegistersRegister Descriptions Flash registers are described in this subsectionCFM Clock Divider Register Cfmclkd Cfmcr Field DescriptionsBits Name Description Divld PRDIV8CFM Security Register Cfmsec Cfmclkd Field DescriptionsCfmsec Field Descriptions SEC150 DescriptionProt CFM Protection Register CfmprotCfmprot Field Descriptions CFM Supervisor Access Register Cfmsacc PROTECT31PROTECT2 SectorData CFM Data Access Register CfmdaccCfmsacc Field Descriptions CFM User Status Register Cfmustat Only one Cfmustat bit should be cleared at a time10. Cfmustat Field Descriptions Cbeif Ccif Pviol Accerr BlankCommand Name Description CFM Command Register Cfmcmd12. Cfmcmd User Mode Commands CFM Operation Read OperationsWrite Operations Program and Erase OperationsConsider the following example for fSYS = 66 MHz Setting the Cfmclkd RegisterThus the Flash state machine clock will be Program, Erase, and Verify Sequences Flash Valid Commands 13summarizes the valid Flash user commands13. Flash User Commands Meaning Description13. Example Program Algorithm Stop Mode Flash User Mode Illegal OperationsMaster Mode Flash Security OperationErase Verify Check ResetBack Door Access Interrupt Source Interrupt Flag Local Enable Interrupts14. CFM Interrupt Sources Cbeif CbeieInterrupts MCF5282 User’s Manual Memory Map and Registers Programming ModelLow-Power Interrupt Control Register Lpicr Chip Configuration Module Memory MapMemory Map Following subsection describes the PMM registersLpicr Field Description EnbstopLow-Power Control Register Lpcr Xlpmipl SettingsXlpmipl Interrupts Level Needed to Exit Low-Power Mode Lpmd Stpmd LvdseLow-Power Modes Low-Power ModesPLL/CLKOUT Stop Mode Operation Functional DescriptionRun Mode Wait ModeDoze Mode Stop ModePeripheral Behavior in Low-Power Modes Static Random-Access Memory SramPeripheral Shut Down ColdFire CoreSdram Controller Sdramc Chip Select ModuleDMA Controller DMAC0-DMA3 Uart Modules UART0, UART1, and UART2Queued Serial Peripheral Interface Qspi DMA Timers DMAT0-DMAT32.9 I2C Module Reset Controller Interrupt Controllers INTC0, INTC1Fast Ethernet Controller FEC 2.14 I/O PortsChip Configuration Module Clock ModuleWatchdog Timer Programmable Interrupt Timers PIT0, PIT1, PIT2 and PIT3Edge Port Queued Analog-to-Digital Converter QadcGeneral Purpose Timers Gpta and Gptb FlexCANFunctional Description ColdFire Flash Module Summary of Peripheral State During Low-Power Modes CPU and Peripherals in Low-Power Modes2.25 BDM JtagJtag QadcBDM Functional Description MCF5282 User’s Manual Features Overview3124 2316 158 Memory Map and Register DefinitionSCM Register Map Cache Register DescriptionsInternal Peripheral System Base Address Register Ipsbar Memory Base Address Register Rambar Ipsbar Field DescriptionMemory Base Address Register Rambar Rambar Field Description BDECrsr Field Descriptions Core Reset Status Register CrsrCore Watchdog Control Register Cwcr Register Descriptions Core Watchdog Timer Delay CWT CWT Time-Out PeriodCore Watchdog Service Register Cwsr Internal Bus ArbitrationFEC Sdramc SRAM1 Mpark Rambar CPU DMA EIMMarb Arbitration Algorithms Round-Robin ModeOverview Fixed Mode Fixed Timeout Prklast LckouttimeBus Master Park Register Mpark M2PEN BCR24BIT M3PRTY M2PRTY M0PRTY M1PRTYMpark Field Description System Access Control Unit Sacu FeaturesMemory Map/Register Definition Sacu Register Memory Map3128 2724 2320 1916 1512 118 PACR1 PACR2 PACR3PACR6 Peripheral Access Control Registers Pacr 0-PACR8Master Privilege Register MPR Ipsbar Offset Name Modules Controlled 12. Peripheral Access Control Registers PACRsBits Supervisor Mode User Mode UART2 QspiDTIM0 DTIM1 DTIM2 DTIM3Gpacr Field Descriptions 13. Grouped PeripheralAccess Control Register14. Gpacr Accessctrl Bit Encodings 15. Gpacr Address Space Register Space Protected Modules Protected Ipsbar OffsetGPACR0 EPORT, WDOG, PIT0-PIT3, QADC, GPTA, GptbNormal PLL Mode Modes of OperationLow-power Mode Operation 2 11 PLL ModeExternal Clock Mode Clock Module Operation in Low-power ModesBlock Diagram Clock Module Block DiagramSignal Descriptions Signal PropertiesExtal Name FunctionMemory Map and Registers Register Descriptions Synthesizer Control Register SyncrLolre MFD2 MFD1 MFD0 Locre Locen Disclk Fwkup STPMD1 STPMD0RFD MFDMFD20 Synthesizer Status Register Synsr StpmdOSC PllmodeSynsr Field Descriptions LocksClock Mode Functional DescriptionSystem Clock Modes System Clock ModesClock Operation During Reset System Clock Mode PLL OptionsSystem Clock Generation Clock Out and Clock In RelationshipsPhase and Frequency Detector PFD PLL OperationCharge Pump Current and MFD in Normal Mode Operation Charge Pump/Loop FilterVoltage Control Output VCO Multiplication Factor Divider MFDPLL Lock Detection PLL Loss of Lock Reset PLL Loss of Lock ConditionsLoss of Clock Reset Loss of Clock DetectionAlternate Clock Selection Loss of Clock SummaryLoss of Clock in Stop Mode 10. Stop Mode Operation Sheet 1Stop 10. Stop Mode Operation Sheet 2Expected PLL Action ‘LC NRM ‘LK 10. Stop Mode Operation Sheet 3NRM ‘LC ‘LK 10. Stop Mode Operation Sheet 4 PLL10. Stop Mode Operation Sheet 5 Lose referenceClock ModesFunctional Description MCF5282 User’s Manual Chapter Interrupt Controller Modules 10.1 68K/ColdFire Interrupt Architecture Overview68K/ColdFire Interrupt Architecture Overview Interrupt Controller Theory of Operation Interrupt RecognitionInterrupt Prioritization Interrupt Priority Within a LevelInterrupt Vector Determination Memory Map Interrupt Controller Base AddressesInterrupt Controller Memory Map Interrupt Controller Number Base AddressInterrupt Pending Registers IPRHn, IPRLn INT Maskall Interrupt Mask Register IMRHn, IMRLnIntmask Intfrc Interrupt Force Registers INTFRCHn, INTFRCLnIMRLn Field Descriptions Interrupt Request Level Register IRLRn IRQInterrupt Acknowledge Level and Priority Register IACKLPRn Interrupt Control Register ICRnx, x = 1, 211. IACKLPRn Field Descriptions Level PRI13. Interrupt Source Assignment for INTC0 Interrupt Sources12. ICRnx Field Descriptions IIF DTIM0 CAP/REFDTIM1 CAP/REF DTIM2 CAP/REFGptb TOF PIT0 PIFPIT1 PIF PIT2 PIFSoftware and Level n Iack Registers SWIACKR, L1IACK-L7IACK 14. Interrupt Source Assignment for INTC1Prioritization Between Interrupt Controllers VectorLow-Power Wakeup Operation 10-18 Ipbus Low-Power Mode OperationIntroduction Interrupt/General-Purpose I/O Pin Descriptions Edge Port Module Operation in Low-power ModesLow-power Mode Eport Operation Mode Exit Edge Port Module Memory Map Bits AccessRegisters Eport Pin Assignment Register Eppar Eport Data Direction Register EpddrEPPA7 EPPA5 EPPA4 EPPA3 EPPA2 EPPA1Epdd Field Descriptions Edge Port Interrupt Enable Register EpierEdge Port Data Register Epdr Epdr Field Descriptions Edge Port Pin Data Register EppdrEdge Port Flag Register Epfr Epfr Field Descriptions EPF7-EPF111-8 Chip Select Module Signals 1lists signals used by the chip select moduleChip Select Module Signals Signal DescriptionD3124 D2316 D158 D70 Byte Enables/Byte Write Enable Signal SettingsTransfer Size Port Size Chip Select Operation General Chip Select OperationExternal Boot Chip Select Operation Accesses by Matches in CSARs and DACRs12.3.1.1 8-, 16-, and 32-Bit Port Sizing BS2 BS1 BS0D1918 External Boot Chip Select Configuration D1918 Boot Device/Data Port SizeChip Select Registers Chip Select RegistersChip Select Module Registers Chip Select Address Registers CSAR0-CSAR6CSARs, -2,specify the chip select base addresses 6describes CsarbaChip Select Mask Registers CSMR0-CSMR6 7describes Csmr fieldsCSARn Field Description Csmr n Field DescriptionsChip Select Control Registers CSCR0-CSCR6 8describes CSCRn fieldsSD,UC PS1 PS0 BEM Bstr BstwCSCRn Field Descriptions No internal TA is asserted. Cycle is terminated externally12-10 Signal Name Description Clkout Edge Bus and Control SignalsColdFire Bus Signal Summary TIP Bus CharacteristicsData Transfer Operation Chip-Select Module Output Timing Diagram Bus Cycle ExecutionAccesses by Matches in CSCRs and DACRs State Cycle Data Transfer Cycle StatesBus Cycle States Read Cycle MCF5282 System3describes the six states of a basic write cycle Write cycle timing diagram is shown in FigureWrite Cycle Fast Termination Cycles Read Cycle with Fast TerminationBack-to-Back Bus Cycles Burst CyclesAllowable Line Access Patterns A32 Longword AccessesLine Transfers Line Read Bus Cycles13shows timing when internal termination is used Line Write Bus Cycles 16. Line Write Burst 2-1-1-1, Internal/External TerminationMisaligned Operands 17shows a line burst write with one wait-state insertion19. Example of a Misaligned Longword Transfer 32-Bit Port 13-16 Chapter Signal Descriptions MCF5282 Block Diagram with Signal Interfaces Sdram Controller Signals MCF5282 Signal DescriptionSignal Name Abbreviation Function External Memory Interface Signal Name Abbreviation Function Clock and Reset SignalsChip Configuration Module External Interrupt SignalsQueued Serial Peripheral Interface Qspi Signals FlexCAN Signals2C Signals Uart SignalsGeneral Purpose Timer Signals DMA Timer SignalsAnalog-to-Digital Converter Qadc Signals Debug Support SignalsPower and Reference Signals 2lists signals in alphabetical order by abbreviated nameTest Signals MCF5282 Alphabetical Signal Index Abbreviation FunctionVddpll TCK MCF5282 Signals and Pin Numbers Sorted by Function Chip Configuration/Mode SelectionSecondary External Memory Interface and PortsChip Selects Sdram ControllerExternal Interrupts Port EthernetFlexCAN General Purpose Timers UARTsDebug and Jtag Test Port Control DMA TimersQueued Analog-to-Digital Converter Qadc Test Single-Chip ModePower Supplies External Boot Mode Listing of signals that do not default to a Gpio functionPin Reset States at Reset Single-Chip Mode Signal Reset Clock and Reset Signals14.2 MCF5282 External Signals External Interface Module EIM SignalsAddress Bus A230 Data Bus D310Output Enable OE Transfer Error Acknowledge TEATransfer Acknowledge TA Read/Write R/WTransfer Start TS Transfer In Progress TIPChip Selects CS60 Transfer Size EncodingSdram Controller Signals Clock and Reset Signals Chip Configuration SignalsExternal Interrupt Signals Ethernet Module SignalsTransmit Error Etxer Collision EcolReceive Clock Erxclk Receive Data Valid ErxdvQueued Serial Peripheral Interface Qspi Signals Uart Module Signals FlexCAN Signals14.2.9 I2C Signals General Purpose Timer Signals DMA Timer Signals Analog-to-Digital Converter Signals Debug Support Signals Breakpoint/Test Mode Select BKPT/TMS Development Serial Input/Test Data DSI/TDIDevelopment Serial Output/Test Data DSO/TDO Test Clock TclkTest Signals Debug Data DDATA30Processor Status Outputs PST30 Test TestPower and Reference Signals 14-34 Overview DefinitionsBlock Diagram and Major Components DACR0DACR1 Scas Sras Scke SDRAMCS10 DramwSdram Controller Operation Sdram CommandsCommand Definition Dram Controller Signals 2describes the behavior of Dram signals in synchronous modeMemory Map for Sdramc Registers Dram controller registers memory map is shown in TableDram Control Register DCR DCR, shown in -2,controls refresh logic4describes DCR fields DCR Field DescriptionsDram Address and Control Registers DACR0/DACR1 5describes DACRn fieldsDACRn Field Descriptions Bit15-7 Bit Associated Access Type Access Definition Dram Controller Mask Registers DMR0/DMR16describes DMRn fields DMRn Field DescriptionsGeneral Synchronous Operation Guidelines Address MultiplexingGeneric Address Multiplexing Scheme Address Pin Row Address Column AddressMCF5282 Pins Row ColumnPins Row Column 15-12 Burst Page Mode Pins MCF5282Sdram Byte Strobe Connections Interfacing ExampleBurst Read Sdram Access Burst Write Sdram Access Auto-Refresh OperationSelf-Refresh Operation Auto-Refresh OperationInitialization Sequence Self-Refresh OperationMode Register Settings 25. Sdram Example Specifications Parameter SpecificationSdram Example ClkoutSdram Interface Configuration DCR InitializationDacr Initialization 26. Sdram Hardware ConnectionsBits Name Setting Description DACRs should be programmed as shown in Figure28. Dacr Initialization Values Casl CBM ImrsDMR Initialization 29. DMR0 Initialization ValuesMode Register Initialization 30. Mode Register Initialization31. Mode Register Mapping to MCF5282 A310 MCF5282 Pins Sdram Pins Mode Register InitializationMode Register Initialization Sequence Initialization CodePrecharge Sequence Refresh Sequence15-25 15-26 Chapter DMA Controller Module DMA Module Features Channel 0 Channel 1 Channel 2 ChannelDMA Request Control Dmareqc DMA Transfer Overview DMADMA Controller Module Programming Model Memory Map for DMA Controller Module RegistersSource Address Registers SAR0-SAR3 Destination Address Registers DAR0-DAR3SAR DARByte Count Registers BCR0-BCR3 BCRDMA Control Registers DCR0-DCR3 3describes DCRn fieldsDCRn Field Descriptions BWC Sinc Ssize Dinc Dsize StartBWC Encoding BCR24BIT =DSR n Field Descriptions DMA Status Registers DSR0-DSR34describes DSRn fields DMA Controller Module Functional Description Transfer Requests Cycle-Steal and Continuous ModesBSY DoneData Transfer Modes Dual-Address TransfersProgramming the DMA Controller Module Channel Initialization and StartupChannel Prioritization Data Transfer Auto-AlignmentTermination Bandwidth Control16-16 Chapter Fast Ethernet Controller FEC Full and Half Duplex Operation Interface Options17.2.2.1 10 Mbps and 100 Mbps MII Interface Primary operational modes are described in this sectionInternal Loopback 17.2.2.2 10 Mpbs 7-Wire Interface OperationAddress Recognition Options FEC Top-Level Functional Diagram PAD17-5 Initialization Sequence User Initialization Prior to Asserting EcretherenHardware Controlled Initialization Ecretheren De-Assertion Effect on FECMicrocontroller Initialization User Initialization After Asserting EcretherenFEC User Initialization Before Ecretheren Microcontroller InitializationMII Mode Wire Mode ConfigurationSignal Description Emac pin Network Interface OptionsFEC Frame Transmission FEC Frame Reception Ethernet Address Recognition Ethernet Address Recognition-Receive Block Decisions Hash Algorithm Ethernet Address Recognitionq-Microcode DecisionsDestination Address to 6-Bit Hash Bit DA Bit Hash Hash Decimal Hex Value17-15 Pause Frame Field Specification Full Duplex Flow ControlInternal and External Loopback Inter-Packet Gap IPG TimeCollision Handling Ethernet Error-Handling Procedure Transmission ErrorsReception Errors HeartbeatTop Level Module Memory Map Detailed Memory Map Control/Status RegistersModule Memory Map 10. FEC Register Memory MapMIB Block Counters Memory Map 11. MIB Counters Memory Map Mnemonic Description OffsetFollowing sections describe each register in detail RegistersEthernet Interrupt Event Register EIR Hberr Ieeetsqe Babr Babt GRA TXF TXB RXF RXB MII Eberr17-25 Babr Babt GRA TXF TXB RXF RXB MII Interrupt Mask Register EimrReceive Descriptor Active Register Rdar Transmit Descriptor Active Register Tdar RdesactiveXdesactive Etheren ResetEthernet Control Register ECR Data MII Management Frame Register Mmfr16. ECR Field Descriptions 17. Mmfr Field Descriptions Bit Name DescriptionDispreamble MII Speed Control Register MscrDispreamble Miispeed Mibdisable Mibidle MibdisableMIB Control Register Mibc 19. Programming Examples for MscrReceive Control Register RCR MaxflFCE Bcrej Prom Miimode DRT Loop FCEGTS Transmit Control Register TCRTfcpause Fden Tfcpause Physical Address Low Register Palr22. TCR Field Descriptions Physical Address High Register Paur PADDR1PADDR2 TypeOpcode/Pause Duration Register OPD Descriptor Individual Upper Address Register Iaur24. Paur Field Descriptions OpcodeDescriptor Individual Lower Address Ialr IADDR1Bits Name Descriptions IADDR2Descriptor Group Upper Address Gaur Descriptor Group Lower Address Galr27. Ialr Field Descriptions GADDR1Xwmrk Fifo Transmit Fifo Watermark Register TfwrGADDR2 Rbound Fifo Receive Bound Register Frbr30. Tfwr Field Descriptions Rfstart Fifo Receive Start Register FrsrReceive Descriptor Ring Start Erdsr Xdesstart Transmit Buffer Descriptor Ring Start EtsdrRdesstart Rbufsize Receive Buffer Size Register Emrbr34. Etdsr Field Descriptions Driver/DMA Operation with Transmit BDs Buffer DescriptorsDriver/DMA Operation with Buffer Descriptors Driver/DMA Operation with Receive BDs Ethernet Receive Buffer Descriptor RxBD RO1 RO236. Receive Buffer Descriptor Field Definitions Word Location Field Name DescriptionRO1 ErdsrEthernet Transmit Buffer Descriptor TxBD TO1 TO2 ABC TO117-51 17-52 Watchdog Module Operation in Low-power Modes Low-power Mode Watchdog Operation Mode ExitRefer to -2for an overview of the watchdog memory map SignalsWatchdog timer module has no off-chip signals Watchdog Control Register WCR 16-bit WCR configures watchdog timer operationWatchdog Timer Module Memory Map Watchdog Modulus Register WMR WCR Field DescriptionsWatchdog Service Register WSR Watchdog Count Register WcntrWMR Field Descriptions WC9 WC8WS9 WS8 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0Chapter Programmable Interrupt Timer Modules PIT0-PIT3 Low-power Mode PIT Operation Mode Exit PIT module has no off-chip signalsPIT Module Operation in Low-power Modes Programmable Interrupt Timer Modules Memory Map Ipsbar Offset Access For PITx Bits AddressPIT Control and Status Register Pcsr PRE3 PRE2 PRE1 PRE0Doze Halted OVW PIE PIF RLD PREPIT Modulus Register PMR PIFThis subsection describes the PIT functional operation Set-and-Forget Timer OperationPIT Count Register Pcntr Free-Running Timer Operation Timeout SpecificationsSystem clock PIT Clock CounterInterrupt Request Flag Enable Bit Timeout Interrupt Operation4shows the interrupt request generated by the PIT PIT Interrupt RequestsChapter General Purpose Timer Modules Gpta and Gptb GPT Block Diagram Signal Description Function Reset State Pull-up Name Register BitGPTn20 PinIpsbar Offset Bits Access GPTn3SYNCn GPT Modules Memory MapGPT Input Capture/Output Compare Select Register Gptios IOSGPT Compare Force Register Gpcforc GPT Output Compare 3 Mask Register GPTOC3MGptios Field Descriptions FOCGPT Output Compare 3 Data Register GPTOC3D GPT Counter Register GptcntGPTOC3M Field Descriptions OC3DGPT System Control Register 1 GPTSCR1 Gptcnt Field DescriptionsGpten Tffca GptenGPT Toggle-On-Overflow Register Gpttov GPT Control Register 1 GPTCTL1TOV OM3 OL3 OM2GPT Interrupt Enable Register Gptie GPT Control Register 2 GPTCTL211. GPTCL1 Field Descriptions EDG3B EDG3A EDG2B EDG2AGPT System Control Register 2 GPTSCR2 13. Gptie Field DescriptionsGPT Flag Register 1 GPTFLG1 GPT Flag Register 2 GPTFLG2GPT Channel Registers GPTCn Pulse Accumulator Control Register GptpactlCcnt PAE Pamod Pedge CLK Paovi PAIPaovf Paif Pulse Accumulator Flag Register GptpaflgPaclk Pacnt Pulse Accumulator Counter Register Gptpacnt19. Gptpaflg Field Descriptions GPT Port Data Register Gptport GPT Port Data Direction Register Gptddr22. Gptddr Field Descriptions PorttOutput Compare PrescalerInput Capture Event Counter Mode Pulse AccumulatorGated Time Accumulation Mode General-Purpose I/O PortsPulse Accumulator OM3 OL3Dir Function 23. GPT Settings and Pin FunctionsEDGx OMx OC3Mx Pin Data Driven Comments Reset 24lists the interrupt requests generated by the timerInterrupt Request Flag Enable Bit InterruptsTimer Overflow TOF GPT Channel Interrupts CnFPulse Accumulator Overflow Paovf Pulse Accumulator Input Paif20-23 20-24 Chapter DMA Timers DTIM0-DTIM3 Prescaler DMA Timer Programming ModelKey Features Capture Mode Output ModeDMA Timer Module Memory Map Reference CompareDMA Timer Mode Registers DTMRn Orri FRR CLK RSTDMA Timer Extended Mode Registers DTXMRn 2describes the DTMRn fieldsDTMRn Field Descriptions DTXMR3DTXMRn Field Descriptions DMA Timer Event Registers DTERn3describes the DTXMRn fields DMA Timer Reference Registers DTRRn DMA Timer Capture Registers DTCRn4describes the DTERn fields DTERn Field DescriptionsUsing the DMA Timer Modules DMA Timer Counters DTCNnCode Example Calculating Time-Out Values T0LOOPChapter Queued Serial Peripheral Interface Qspi Module Module DescriptionQspiclk Interface and SignalsQspi RAM Qspi Input and Output Signals and Functions Signal Name Hi-Z or Actively Driven FunctionOperation Internal Bus InterfaceQspi RAM Receive RAM Relative Address Register 0x000x01 0x0FTransmit RAM Command RAMBaud Rate Selection Transfer Delays Qspiclk Frequency as Function of System Clock and Baud RateSystem Clock 66.67 MHzTransfer Length Programming Model Qspi RegistersQspi Mode Register QMR 4gives QMR field descriptionsQMR Field Descriptions Value Bits per transferQspi Delay Register Qdlyr Qspics Qmrcpol =Qmrcpha = = Qdlyrqcd Qcrcont = = Qdlyrdtl QCDQspi Wrap Register QWR 5gives Qdlyr field descriptions6gives QWR field descriptions Qdlyr Field DescriptionsQIR Field Descriptions Qspi Interrupt Register QIR7describes QIR fields Addr Qspi Address Register QARQspi Data Register QDR QCR0-QCR15 Field Descriptions Command RAM Registers QCR0-QCR158gives QCR field descriptions Programming Example QSPICS30Qspiclk QS2 Qspidout QS3 Qspidin QS4 QS522-17 22-18 Uart Ucts Urts Urxd UtxdSerial Module Overview Ipsbar Offset 3124 2316 158 Register DescriptionsUart Module Memory Map Uart Mode Registers 1 UMR1n ERRParity Mode Parity Type PT= 2describes UMR1n fieldsUMR1n Field Descriptions CTSUMR2 n Field Descriptions Uart Mode Register 2 UMR2n3describes UMR2n fields Uart Status Registers USRn 4describes USRn fieldsUMR2n Field Descriptions USRn Field DescriptionsRCS TCS Uart Clock Select Registers UCSRn5describes UCSRn fields Uart Command Registers UCRn UCSRn Field DescriptionsRCS DtinBits Value Command Description UCR n Field DescriptionsUCRn Field Descriptions Uart Receive Buffers URBnUart Transmit Buffers UTBn Uart Input Port Change Registers UIPCRn 7describes UIPCRn fieldsUipcr n Field Descriptions COS CTSUACRs, shown in -7,control the input enable Uart Auxiliary Control Register UACRnUart Interrupt Status/Mask Registers UISRn/UIMRn 8describes UACRn fieldsUisr n/UIMR n Field Descriptions Uart Baud Rate Generator Registers UBG1n/UBG2n9describes UISRn and UIMRn fields Uart Output Port Command Registers UOP1n/UOP0n Uart Input Port Register UIPn10describes UIPn fields 11describes UOP1 and UOP0 fields11. UOP1/UOP0 Field Descriptions Ucts Uart Module Signal DefinitionsIRQ Programmable Divider 12. Uart Module SignalsTransmitter/Receiver Clock Source Following sections describe how to calculate baud rates Calculating Baud RatesSystem Clock Baud Rates SysclkTransmitter and Receiver Operating Modes TransmitterTherefore UBG1n = 0x00 and UBG2n = 0xD6 External Clock23-21 20. Transmitter Timing Diagram ReceiverFifo Stack 21shows receiver functional timing23-24 Looping Modes Automatic Echo ModeLocal Loop-Back Mode Multidrop Mode Remote Loop-Back Mode25. Multidrop Mode Timing Diagram Bus Operation ProgrammingRead Cycles Write CyclesSetting up the Uart to Generate Core Interrupts Setting up the Uart to Request DMA ServiceInterrupt and DMA Request Initialization 13. Uart InterruptsRegister Setting Uart Module Initialization Sequence15shows the Uart module initialization sequence 14. Uart DMA Requests26. Uart Mode Programming Flowchart Sheet 1 26. Uart Mode Programming Flowchart Sheet 2 26. Uart Mode Programming Flowchart Sheet 3 26. Uart Mode Programming Flowchart Sheet 4 26. Uart Mode Programming Flowchart Sheet 5 23-36 Interface Features Chapter I2C InterfaceAcknowledge bit generation/detection Bus-busy detection IfdrIadr SCL SDA24.3 I2C System Configuration 24.4 I2C ProtocolArbitration Procedure Repeated StartClock Synchronization HandshakingClock Stretching SCL1 SCL224.5.1 I2C Address Register I2ADR 2describes I2ADR fieldsI2C Interface Memory Map I2ADR Field Descriptions24.5.2 I2C Frequency Divider Register I2FDR 3describes I2FDRICI2FDR Field Descriptions Divider24.5.3 I2C Control Register I2CR 4describes I2CR fieldsI2CR Field Descriptions IEN Iien24.5.4 I2C Status Register I2SR 5describes I2SR fieldsI2SR Field Descriptions ICF Iaas IBB IAL SRW IIF24.6 I2C Programming Examples 24.5.5 I2C Data I/O Register I2DRGeneration of Start Post-Transfer Software Response24.6.4 Generation of Stop I2SRSlave Mode Generation of Repeated StartArbitration Lost RXAK= IAAS=1SRW=1 Write24-16 Chapter FlexCAN RAM MB3 MB2 MB1 MB0 Cantx CanrxFlexCAN Memory Map 25.1.2 External SignalsFlexCAN Memory Map Can System Message BuffersMessage Buffer Structure Typical can system is shown below in FigureCommon Fields for Extended and Standard Format Frames Message Buffer Codes for Transmit Buffers Common Extended/Standard Format FramesMessage Buffer Codes for Receive Buffers Message Buffer Memory Map Fields for Extended Format FramesFields for Standard Format Frames Extended Format FramesIdhigh Idlow Functional OverviewMessage Buffers Transmit Process Receive ProcessMessage Buffer Handling Self-Received FramesReceive Message Buffer Deactivation Serial Message Buffers SMBsTransmit Message Buffer Deactivation Remote Frames Locking and Releasing Message BuffersTime Stamp Listen-Only ModeOverload Frames Configuring the FlexCAN Bit Timing Bit TimingExamples of System Clock/CAN Bit-Rate/S-Clock Freq Mhz Time-quanta/bit Value +FlexCAN Error Counters FlexCAN Initialization Sequence Special Operating Modes Debug ModeLow-Power Stop Mode for Power Saving Canmcr Auto-Power Save Mode InterruptsCan Module Configuration Register Canmcr Programmer’s Model8describes the Canmcr fields Stop FRZ Halt Notrdy Wakemsk Softrst FrzackCanmcr Field Descriptions StopFlexCAN Control Register 0 CANCTRL0 9describes the CANCTRL0 fields10. Transmit Pin Configuration Transmit Pin ConfigurationFlexCAN Control Register 1 CANCTRL1 11describes the CANCTRL1 fieldsPrescaler Divide Register Presdiv 12describes the Presdiv fields11. CANCTRL1 Field Descriptions SampFlexCAN Control Register 2 CANCTRL2 13describes the CANCTRL2 fields12. Presdiv Field Descriptions 13. CANCTRL2 Field DescriptionsFree Running Timer Timer 14describes the Timer fields14. Timer Field Descriptions Rx Mask RegistersReceive Mask Registers RXGMASK, RX14MASK, RX15MASK 12. Rx Mask Registers RXGMASK, RX14MASK, and RX15MASK16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions FlexCAN Error and Status Register Estat17describes the Estat fields 17. Estat Field Descriptions BiterrInterrupt Mask Register Imask 18describes the Imask fieldsBUF15M BUF14M BUF13M BUF10M BUF9M BUF8MInterrupt Flag Register Iflag 19describes the Iflag fields18. Imask Field Descriptions 19. Iflag Field DescriptionsFlexCAN Receive Error Counter Rxectr FlexCAN Transmit Error Counter Txectr20describes the Rxectr fields 21describes the Txectr fieldsChapter General Purpose I/O Module MCF5282 Ports Module Block Diagram Features Sdram control Bit DMA timers Uart transmit/receiveOverview Modes of OperationExternal Signal Description MCF5282 Ports External SignalsErxer SDASCL UCTS031-24 23-16 15-8 Access Memory Map/Register DefinitionRegister Overview MCF5282 Ports Module Memory MapDdrb Ddrc Ddreh DdrelClra Clrb Clrc Clrd Clre Clrf Clrg ClrhPort Output Data Registers PORTn Port Output Data Registers 8-bitPort Data Direction Registers DDRn PORTn bits are described in TablePORTn 8-bit, 7-bit, 6-bit, and 4-bit Field Descriptions Register Bits Name DescriptionPort Data Direction Register 7-bit Port Pin Data/Set Data Registers PORTnP/SETn 10. Port Pin Data/Set Data Registers 8-bitPort Clear Output Data Registers CLRn PORTnP/SETn bits are described in TablePORTnP/SETn 8-bit, 6-bit, and 4-bit Field Descriptions PORTUAP/SETUACLRn register bits are described in Table CLRn 8-bit,7-bit, 6-bit, and 4-bit Field DescriptionsReset Values for Pbcdpar Bits Port Size Pbpa Reset Pcdpa ResetExternal Boot Port B/C/D Pin Assignment Register PbcdparPEPA3 Port E Pin Assignment Register PeparPepar Field Descriptions 10. Reset Values for Pepar Bits and Fields Single chip mode11. Pfpar Field Descriptions Port F Pin Assignment Register PfparPfpar controls the pin function of port F75 12. Pjpar Field Descriptions Port J Pin Assignment Register PjparPjpar controls the pin function of port J Port SD Pin Assignment Register Psdpar Port AS Pin Assignment Register PasparPsdpar controls the pin function of port SD Paspar controls the pin function of port ASPort EH/EL Pin Assignment Register Pehlpar 14. Paspar Field DescriptionsPort QS Pin Assignment Register Pqspar Pqspar controls the pin function of port QS15. Pehlpar Field Descriptions ECOL, ERXCLK, ERXDV, ERXD0, EcrsPTCPA3 PTCPA2 PTCPA1 PTCPA0 Port TC Pin Assignment Register PtcparPtcpar controls the pin function of port TC PTDPA3 PTDPA2 PTDPA1 PTDPA0 Port TD Pin Assignment Register PtdparPtdpar controls the pin function of port TD Port UA Pin Assignment Register Puapar Puapar controls the pin function of port UAPort Digital I/O Timing Clkout Input PIN Register PIN DataInitialization/Application Information Clkout Output Data Register Output PINChapter Queued Analog-to-Digital Converter Qadc Qadc Block Diagram Debug Mode Modes of OperationPort QA Signal Functions Port QA Analog Input SignalsPort QB Analog Input Signals Port QB Signal FunctionsPort QA Digital Input/Output Signals External Trigger Input Signals Multiplexed Address Output SignalsMultiplexed Analog Input Signals Port QB Digital I/O SignalsVoltage Reference Signals Dedicated Analog Supply SignalsDedicated Digital I/O Port Supply Signal Multiplexed Analog Input ChannelsQadc Memory Map Qadc Module Configuration Register QadcmcrThis subsection describes the Qadc registers Qadc Test Register Qadctest Port Data Registers Portqa and PortqbPort QA and QB Data Direction Register Ddrqa and Ddrqb ANZ ANY ANX ANWThis subsection describes the Qadc control registers Control RegistersQadc Control Register 0 QACR0 Qadc Control Register 0 QACR0 QACR0 Field Descriptions QPR6Divisor Prescaler fSYS Divide-by ValuesQPR60 CIE1 Qadc Control Register 1 QACR1CIE1 PIE1 SSE1 Operating Mode Queue 1 Operating ModesQadc Control Register 2 QACR2 CIE2 PIE2 SSE2 ResumeQACR2 Field Descriptions Queue 2 Operating ModesCIE2 BQ2Status Registers Qadc Status Register 0 QASR0This subsection describes the Qadc status registers MQ2128 Operating Modes27-20 Queued Analog-to-Digital Converter Qadc 27-21 QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0 CF1 PF1 CF2QS9 QS8 Scan Mode Queue Operation PF Asserts? 10. QASR0 Field Descriptions11. CCW Pause Bit Response CWP12. Queue Status Queue 1/Queue 2 States12. Queue Status Transition Conversion Command Word Table CCW Qadc Status Register 1 QASR1BYP IST1 IST0Non-Multiplexed Input Signals Channel Number Port Signal Name15. Input Sample Times IST10 Input Sample Times17. Multiplexed Channel Assignments and Signal Designations Multiplexed Input Signals Channel NumberResult Registers Right-Justified Unsigned Result Register RjurrLeft-Justified Signed Result Register Ljsrr Left-Justified Unsigned Result Register Ljurr18. Rjurr Field Descriptions ResultExternal Multiplexing 27.7 Functional DescriptionResult Coherency External Multiplexing Operation 18. External Multiplexing Configuration Analog Subsystem Module Version OptionsAnalog-to-Digital Converter Operation 21. Analog Input Channels19. Qadc Analog Subsystem Block Diagram Conversion Cycle TimesChannel Decode and Multiplexer Sample BufferDigital Control Subsystem ComparatorBias Successive Approximation Register SARQueue Priority Timing Examples Queue Priority22. Qadc Queue Operation with Pause Queue Priority Schemes 22. Trigger Events23. Status Bits Events23. CCW Priority Situation 24. CCW Priority Situation 26. CCW Priority Situation 28. CCW Priority Situation 30. CCW Priority Situation 32. CCW Priority Situation 34. CCW Freeze Situation 38. CCW Freeze Situation Boundary Conditions Disabled Mode Reserved ModeScan Modes Single-Scan ModesSoftware-Initiated Single-Scan Mode Externally Triggered Single-Scan Mode Externally Gated Single-Scan ModeInterval Timer Single-Scan Mode Continuous-Scan Modes Software-Initiated Continuous-Scan Mode Externally Triggered Continuous-Scan Mode Externally Gated Continuous-Scan ModePeriodic Timer Continuous-Scan Mode Qadc Clock Qclk GenerationPeriodic/Interval Timer 42. Qadc Clock Subsystem FunctionsConversion Command Word Table 43illustrates the operation of the queue structure43. Qadc Conversion Queue Operation Queued Analog-to-Digital Converter Qadc 27-61 Signal Connection Considerations Result Word TableAnalog Reference Signals Analog Power Signals45. Errors Resulting from Clipping Conversion Timing Schemes46. External Positive Edge Trigger Mode Timing with Pause 47. Gated Mode, Single Scan Timing Analog Supply Filtering and Grounding 48. Gated Mode, Continuous Scan Timing49. Star-Ground at the Point of Power Supply Origin 50. Input Signal Subjected to Negative Stress Accommodating Positive/Negative Stress ConditionsIinjn IinjpAnalog Input Considerations 52. External Multiplexing of Analog Signal Sources Analog Input Pins 53. Electrical Model of an A/D Input SignalSource Resistance RF + Rsrc 100 Ω 10 kΩ 100 kΩ Settling Time for the External Circuit24. External Circuit Settling Time to 1/2 LSB Interrupt Operation Error Resulting from Leakage25. Error Resulting from Input Leakage IOff Interrupt Sources 26. Qadc Status Flags and Interrupt SourcesQueue Queue Activity Status Interrupt Flag PF1 PIE1Chapter Reset Controller Module Reset Controller Signal Properties RstiRsto Name Direction InputReset Control Register RCR Reset Controller Memory MapReset Status Register RSR LvdfLvdie Soft WDR PORRSR Field Descriptions WDRReset Sources Power-On ResetReset Source Summary Source TypeExternal Reset Watchdog Timer ResetLoss-of-Clock Reset Loss-of-Lock ResetReset Control Flow Reset Control Flow Concurrent Resets Synchronous Reset RequestsInternal Reset Request Power-On Reset/Low-Voltage Detect ResetReset Status Flags 28-12 Debug module is shown in Figure Processor/Debug Module InterfaceSignal Description Debug Module SignalsPST30 Definition Hex Real-Time Trace SupportProcessor Status Encoding Begin Execution of Taken Branch PST = PST30 Definition Hex BinaryClkout PST DdataAatr AblrAbhr CSRRevision a Shared Debug Resources BDM/Breakpoint RegistersRev. a Shared BDM/Breakpoint Hardware DRc4-0 Register Name Abbreviation Initial StateAddress Attribute Trigger Register Aatr 5describes Aatr fieldsAatr Field Descriptions TMMAddress Breakpoint Registers ABLR, Abhr Address Breakpoint Registers ABLR, AbhrConfiguration/Status Register CSR 6describes Ablr fields7describes Abhr fields Ablr Field Description8describes CSR fields CSR Field DescriptionsData Breakpoint/Mask Registers DBR, Dbmr IPI10describes Dbmr fields Program Counter Breakpoint/Mask Registers PBR, Pbmr9describes DBR fields Trigger Definition Register TDR 12describes PBR fields13describes Pbmr fields 12. PBR Field Descriptions14describes TDR fields 14. TDR Field DescriptionsBackground Debug Mode BDM CPU HaltEdum Eduu29-17 DSO BDM Serial InterfaceClkout Dsclk DSI Receive Packet Format Transmit Packet Format15describes receive BDM packet fields 16describes transmit BDM packet fieldsSection Command BDM Command Set17. BDM Command Summary ColdFire BDM Command Format 18describes BDM fieldsExtension Words as Required 18. BDM Field DescriptionsCommand Sequence Diagrams 16. Command Sequence DiagramRead A/D Register RAREG/RDREG Command Set DescriptionsCommand Sequence Write A/D Register WAREG/WDREG Read Memory Location Read21. Read Command/Result Formats 22. Read Command Sequence23. Write Command Format Write Memory Location WriteDump Memory Block Dump Set is returned if a bus error occursOperands are sent as 16 and 32 bits, respectively 25. Dump Command/Result Formats 26. Dump Command Sequence Fill Memory Block Fill27. Fill Command Format 28. Fill Command SequenceResume Execution GO No Operation NOP19. Control Register Map Read Control Register RcregRc encoding BDM Accesses of the Stack Pointer Registers A7 SSP, USP BDM Accesses of the Emac Registers35. Wcreg Command/Result Formats Write Control Register WcregRead Debug Module Register Rdmreg 20shows the definition of DRc encodingDRc40 Debug Register Definition Mnemonic Initial State Write Debug Module Register Wdmreg20. Definition of DRc Encoding-Read Real-Time Debug Support Theory of Operation21. DDATA30/CSRBSTAT Breakpoint Response Breakpoint StatusEmulator Mode Concurrent BDM and Processor Operation 22. PST/DDATA Specification for User-Mode Instructions Processor Status, Ddata DefinitionUser Instruction Set Instruction Operand Syntax29-41 29-42 23. PST/DDATA Specification for MAC Instructions 24. PST/DDATA Specification for Supervisor-Mode Instructions Supervisor Instruction SetReset DSI Motorola-Recommended BDM PinoutGND Dsclk GND PST3 PST2 PST1 PST0 DDATA3 DDATA2 DDATA1 DDATA029-46 Chapter Chip Configuration Module CCM Single-Chip Mode Chip Configuration Module Block DiagramSignal Descriptions 30.4.3 D2624, 21, 1916 Reset Configuration Override1provides an overview of the CCM signals RconWrite-Once Bits Read/Write Accessibility Configuration Read/Write AccessChip Configuration Register CCR Following subsection describes the CCM registersSzen BMTReset Configuration Register Rcon BootpsRcsc Rpllsel Rpllref RcscRcsc Chip Select Configuration Bootps Port Size ConfigurationChip Select Configuration Boot Port SizePIN PRN Reset ConfigurationChip Identification Register CIR Reset Configuration Pin States During Reset 10. Configuration During ResetD2524 Chip Mode SelectionClock Mode Boot Device Selection Output Pad Strength ConfigurationClock Mode Selection 11. Chip Configuration Mode SelectionCCM does not generate interrupt requests Chip Select Configuration13. Clock Mode Selection Chapter Ieee 1149.1 Test Access Port Jtag Jtag Block Diagram External Signal Description 31.3.1 Detailed Signal DescriptionJtagen Jtag Enable Pin Function Selected31.3.1.3 TMS/BKPT Test Mode Select / Breakpoint TRST/DSCLK Test Reset / Development Serial ClockSignal State to the Disable Module Tclk Test Clock InputMemory Map/Register Definition Memory MapInstruction Shift Register IR Idcode RegisterBypass Register Jtagcfmclkdiv RegisterTestctrl Register Boundary Scan RegisterJtag Module TAP ControllerJtag Instructions 5describes public and private instructionsJtag Instructions Instruction IR30 Instruction SummarySAMPLE/PRELOAD Instruction External Test Instruction ExtestIdcode Instruction Enabletestctrl Instruction Lockoutrecovery InstructionTestleakage Instruction Highz InstructionInitialization/Application Information RestrictionsClamp Instruction Bypass InstructionNonscan Chain Operation Chapter Mechanical Data Pinout MCF5282 Pinout 256 MapbgaSecondary Tertiary MCF5282 Signal Description by Pin NumberMapbga Pin Pin Functions PG4 PG3PG2 PF4PUA1 VDD GPTB0GPTA0 PQA3 ETRIG1 VRH VDD Vssa VSSPQA0 MA0 VDD Vdda PUA3 VSS Xtal JtagenGPTB2 PQS5Orderable Part Numbers Motorola Part Description Speed TemperatureOrdering Information 32-8 Absolute Maximum Ratings1 Rating Symbol Value UnitMaximum Ratings Rating Symbol HBMThermal Characteristics Thermal CharacteristicsCharacteristic Symbol Value Unit 2lists thermal resistance valuesDC Electrical Specifications DC Electrical Specifications1Characteristic Symbol Min Max Unit Solving equations 1 and 2 for K givesWait Doze Stop Phase Lock Loop Electrical Specifications PLL Electrical SpecificationsQadc Electrical Characteristics Qadc Electrical Specifications OperatingParameter Symbol Min Max Unit Qadc Absolute Maximum RatingsParameter Symbol Min IOH = TBDFlash Memory Characteristics Qadc Conversion Specifications OperatingSgfm Flash Program and Erase Characteristics Num Parameter Symbol Min Max Unit10. Processor Bus Input Timing Specifications External Interface Timing CharacteristicsSgfm Flash Module Life Characteristics Processor Bus Output Timing Specifications 11. External Bus Output Timing SpecificationsName Characteristic Symbol Min Max Unit Control Outputs Timings listed in -10are shown in FigureData Outputs Read/Write Internally Terminated Timing Read Bus Cycle Terminated by TA Read Bus Cycle Terminated by TEA Symbol Min Max Unit Sras Scas DramwSras SCAS1 Dramw 33.9 General Purpose I/O Timing13. Gpio Timing1 Reset and Configuration Override Timing 14. Reset and Configuration Override Timing33.11 I2C Input/Output Timing Specifications 15. I2C Input Timing Specifications between SCL and SDANum Characteristic Min Max Units Clkout Rsti RstoFast Ethernet AC Timing Specifications 16. I2C Output Timing Specifications between SCL and SDAMII Receive Signal Timing ERXD30, ERXDV, ERXER, and Erxclk MII Transmit Signal Timing ETXD30, ETXEN, ETXER, Etxclk17. MII Receive Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing Ecrs and Ecol 19lists MII asynchronous inputs signal timing18. MII Transmit Signal Timing 19. MII Async Inputs Signal TimingMII Serial Management Channel Timing Emdio and Emdc 20. MII Serial Management Channel TimingDMA Timer Module AC Timing Specifications Qspi Electrical Specifications21lists timer module AC timings 22lists Qspi timingsJtag and Boundary Scan Timing 23. Jtag and Boundary Scan Timing17. Test Access Port Timing 16. Boundary Scan Jtag TimingClkout VIL Debug AC Timing Specifications24. Debug AC Timing Specification 20shows real-time trace timing for the values in Table 20. Real-Time Trace AC TimingTable A-1. CPU Space Register Memory Map Address Name Mnemonic SizeACR0 ACR1Table A-2. Module Memory Map Overview Address Module SizeI2C QadcTable A-3. Register Memory Map Address Name Mnemonic Size SCM RegistersSdramc Registers Chip Select RegistersDMA Registers Uart Registers UISR1 UIMR1UBG21 UIP01Qspi Registers DMA Timer RegistersI2C Registers Interrupt Controller Ipsbar + 0xC56 SWACKR0 IPRH1IPRL1 IMRH1Global Interrupt Acknowledge Cycle Registers FEC RegistersGpio Registers Portas PortqsPortsd PorttcPortap Seta Ipsbar +Portbp Setb Ipsbar +Clra ClrfClrg ClrasClock Module Registers Edge Port RegistersWatchdog Timer Registers General Purpose Timer a Registers Qadc RegistersGeneral Purpose Timer B Registers FlexCAN Registers Flash Registers MCF5282 User’s Manual Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14 Index-15 Index-16