Motorola MCF5282, MCF5281 user manual Bypass Register, Jtagcfmclkdiv Register, Testctrl Register

Memory Map/Register Definition

		Table 31-4. IDCODE Register Field Descriptions
Bits	Name	Description
31–28	PRN	Part revision number. Indicate the revision number of the project.
27–22	DC	Design center.
21–12	PIN	Part identification number. Indicate the device number.
11–1	JEDEC	Joint electron device engineering council ID bits. Indicate the reduced JEDEC ID for Motorola.
0	ID	IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the
		bypass register according to the IEEE standard 1149.1.

31.4.2.3 Bypass Register

The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS instruction is selected.

31.4.2.4 JTAG_CFM_CLKDIV Register

The JTAG_CFM_CLKDIV register is a 7-bit clock divider for the CFM that is used with the LOCKOUT_RECOVERY instruction. It controls the period of the clock used for timed events in the CFM erase algorithm. The JTAG_CFM_CLKDIV register must be loaded before the lockout sequence can begin.

31.4.2.5 TEST_CTRL Register

The TEST_CTRL register is a 3-bit shift register path from TDI to TDO when the ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold register on the rising edge of TCLK when the TAP state machine is in the update-DR state.

31.4.2.6 Boundary Scan Register

The boundary scan register is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins, and selects a logic value and direction for bidirectional pins or high impedance for tri-stated pins.

The boundary scan register contains bits for bonded-out and non bonded-out signals excluding JTAG signals, analog signals, power supplies, compliance enable pins, and clock signals.

31-6 MCF5282 User’s Manual MOTOROLA