Motorola MCF5282, MCF5281 user manual Organization

Organization

•Chapter 4, “Cache,” describes the MCF5282 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures.

•Chapter 5, “Static RAM (SRAM),” describes the MCF5282 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples of how to minimize power consumption when using the SRAM.

•Chapter 6, “ColdFire Flash Module (CFM)” describe the functionality of the MCF5282 Flash memory.

•Chapter 7, “Power Management,” describes the low power operation of the MCF5282 and peripheral behavior in low power modes.

•Chapter 8, “System Control Module (SCM),” describes the functionality of the SCM, which provides the programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit Core Watchdog Timer (CWT), and the system control registers and logic.

•Chapter 9, “Clock Module,” describes the MCF5282’s different clocking methods. It also describes clock module operation in low power modes.

•Chapter 10, “Interrupt Controller Modules,” describes operation of the interrupt controller portion of the SCM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme.

•Chapter 11, “Edge Port Module (EPORT),” describes EPORT module functionality, including operation in low power mode.

•Chapter 12, “Chip Select Module,” describes the MCF5282 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers.

•Chapter 13, “External Interface Module (EIM),” describes data-transfer operations, error conditions, bus arbitration, and reset operations.

•Chapter 14, “Signal Descriptions,” describes MCF5282 signals. It includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used.

•Chapter 15, “Synchronous DRAM Controller Module,” describes the configuration and operation of the SDRAM controller. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous operations.

•Chapter 16, “DMA Controller Module,” describes the MCF5282 Direct Memory Access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.

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