Motorola MCF5281, MCF5282 Functional Description, Result Coherency, External Multiplexing

Functional Description

Field

Reset

R/W:

Address

7	6	5	0
	RESULT		—
			Undefined
	R/W		R

IPSBAR + 0x19_0380, 0x19_03fe

Figure 27-17. Left-Justified Unsigned Result Register (LJURR)

Table 27-20. LJURR Field Descriptions

	Bit(s)	Name	Description
	15–6	RESULT	The conversion result is unsigned, left-justified data.
	5–0	—	Reserved, should be cleared.
27.7		Functional Description

This subsection provides a functional description of the QADC.

27.7.1 Result Coherency

The QADC supports byte and half-word reads and writes across a 16-bit data bus interface. All conversion results are stored in half-word registers, and the QADC does not allow more than one result register to be read at a time. For this reason, the QADC does not guarantee read coherency.

Specifically, this means that while the QADC is operating, the data in the result registers can change from one read to the next. Simply initiating a read of one result register will not prevent another from being updated with a new conversion result.

Thus, to read any given number of result registers coherently, the queue or queues capable of modifying these registers must be inactive. This can be guaranteed by system operating conditions (such as, known completion of a software-initiated queue single-scan or no possibility of an externally triggered/gated queue scan) or by simply disabling the queues (writing MQ1 and/or MQ2 to 0).

27.7.2 External Multiplexing

External multiplexer chips concentrate a number of analog signals onto a few QADC inputs. This is useful for applications that need to convert more analog signals than the QADC converter can normally support. External multiplexing also puts the multiplexed chip closer to the signal source. This minimizes the number of analog signals that need to be shielded due to the proximity of noisy high speed digital signals at the microcontroller chip.

MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-31