Motorola MCF5282, MCF5281 user manual CFM Security Register Cfmsec, Cfmclkd Field Descriptions

Memory Map

Table 6-5. CFMCLKD Field Descriptions

Bits	Name		Description
7	DIVLD	Clock divider loaded
		1	CFMCLKD has been written since the last reset.
		0	CFMCLKD has not been written.
6	PRDIV8	Enable prescaler divide by 8
		1	Enables a prescaler that divides the CFM clock by 8 before it enters the CFMCLKD
			divider.
		0	The CFM clock is fed directly into the CFMCLKD divider.
5–0	DIV	Clock divider field. The combination of PRDIV8 and DIV[5:0] effectively divides the CFM
		input clock down to a frequency between 150 kHz and 200 kHz. The frequency range of the
		CFM clock is 150 kHz to 102.4 MHz.

NOTE

CFMCLKD must be written with an appropriate value before programming or erasing the Flash array. Refer to Section 6.4.3.1, “Setting the CFMCLKD Register.”

6.3.4.3CFM Security Register (CFMSEC)

The CFMSEC controls the Flash security features.

NOTE

Enabling Flash security will disable BDM communications.

NOTE

When Flash security is enabled, the chip will boot in single-chip mode regardless of the external reset configuration.

31		30	29	16
Field	KEYEN	SECSTAT		—
Reset				See Note
R/W				R
15				0

Field

Reset

R/W

Address

SEC

See Note

R

IPSBAR + 0x1D_0008

Note: The SECSTAT bit reset value is determined by the security state of the Flash. All other bits in the register are loaded at reset from the Flash Security longword stored at the array base address + 0x0000_0414.

Figure 6-6. CFM Security Register (CFMSEC)

6-10 MCF5282 User’s Manual MOTOROLA