Motorola MCF5281, MCF5282 user manual Example of a Misaligned Longword Transfer 32-Bit Port

Misaligned Operands

misaligned at an odd address, and a longword is misaligned at an address not a multiple of four. Although the MCF5282 enforces no alignment restrictions for data operands (including program counter (PC) relative data addressing), additional bus cycles are required for misaligned operands.

Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch a misaligned instruction word causes an address error exception.

The MCF5282 converts misaligned, cache-inhibited operand accesses to multiple aligned accesses. Figure 13-19shows the transfer of a longword operand from a byte address to a 32-bit port. In this example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1. The slave device supplies the byte and acknowledges the data transfer. When the MCF5282 starts the second cycle, SIZ[1:0] specify a word transfer with a byte offset of 0x2. The next two bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte offset is now 0x0, the port supplies the final byte, and the operation is complete.

31	24 23	16 15		8 7		0	A[2:0]
Transfer 1	—	Byte 0	—		—		001
Transfer 2	—	—	Byte 1		Byte 2		010
Transfer 3	Byte 3	—	—		—		100

Figure 13-19. Example of a Misaligned Longword Transfer (32-Bit Port)

If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the cache. The example in Figure 13-20differs from that in Figure 13-19in that the operand is word-sized and the transfer takes only two bus cycles.

31	24	23	16 15	8 7	0	A[2:0]
Transfer 1	—		—	—	Byte 0	001
Transfer 2	Byte 1		—	—	—	100

Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port)

MOTOROLA Chapter 13. External Interface Module (EIM) 13-15